Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-05-11
2001-09-18
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185220, C365S185240, C365S185190
Reexamination Certificate
active
06292398
ABSTRACT:
TECHNICAL FIELD
The present invention refers to a method for the in-writing verification of the value of the threshold voltage in non-volatile memories and particularly in flash cells.
BACKGROUND OF THE INVENTION
The market demand for non-volatile memories with higher and higher memory capacity imposes on the manufacturers of semiconductors a continuous effort in the reduction of the dimension of the devices and in the increase of the density of stored data.
In order to increase the information storage capacity in a flash memory, that is, in memory cells that maintain their programming state even in the absence of the supply voltage, without necessarily decreasing the physical dimensions of the single cells, the cells must be programmed in such a way that they are able to memorize more than one bit of information, that is the memory cell must be able to have m=2
n
different states or programming levels, where n represents the number of bits that can be memorized in the memory cell. This cell is called “multilevel memory cell”, where each level corresponds to a different value of the threshold voltage of the transistor making up the cell.
The discrimination of the different m programming levels requires a greater precision in the operations of writing and reading. The stage of writing is realized, for instance, in a such way that memory cell is programmed in one of the different m levels by adequately adjusting its threshold voltage in such a way that, when the memory cell is biased at the desired threshold, during the stage of reading, said cell absorbs a corresponding power at the pre-established level of threshold voltage.
Two reading techniques have been proposed for multilevel memory cells: parallel reading and serial reading.
The parallel reading provides for the generation of m−1 predetermined and distinct reference voltages or currents (current references for the current approach, or voltage references for the voltage approach) and the execution of m−1 simultaneous comparisons of such m−1 distinct reference voltages or currents with a current (or a voltage) derived from the memory cell that is to be read.
The advantages of this technique are the high speed and the independence of the reading time from the programming state of the memory cell; a disadvantage is the large area required by the reading circuit, because m−1 separate comparison circuits are necessary to carry out the m−1 simultaneous comparisons.
The serial reading, instead, requires one single reference (current or voltage) that can be varied according to the prescribed law. This single reference is used in order to carry out a series of subsequent comparisons, and it is varied in order to approximate the voltage or the current that is derived from the memory cell that must be read. The advantage of this technique is that it has a simple circuit realization and the area required is small.
It is evident that the time required for the reading of a memory cell is not uniform, but it depends on the particular programming level of the memory cell and on the starting value of the reference voltage (or current) (the reading time depends on the distance between the programming level of the cell that is to be read and the starting value of the reference voltage or current): in order to determine the programming state of a memory cell at m levels a minimum of one to a maximum of m−1 steps of comparison can be necessary. The reading time soon becomes excessive with the increase of the number of bits that are memorized in a single memory cell.
Therefore, it becomes necessary to speed up all the operations of writing, reading and erasing in such a way that it is possible to meet the specifications of the internationally defined standards for the realization of bulk storage devices that replace the magnetic disk.
In particular a cause for the slowing in the operation of writing is the stage of the verification. In fact, this stage, in addition to providing adequate programming pulses, consists in the continuous control of the value of the threshold voltage that is obtained, while verifying that it is the desired one, after a certain number of pulses have been applied to same cell.
The number of verifications depends on the programming algorithm that is used. In an verification algorithm of the “programming and verification pulse” type (suitable to the multilevel programming of floating gate non-volatile memory cells), the operation of control is carried out after each programming pulse. Instead, by increasing the complexity of the circuitry it is possible to compare directly or indirectly the voltage drop between the gate and source electrodes of the memory cell, which is the value of the memorized voltage threshold, with the desired voltage value, while decreasing the number of verifications to be carried out in order to determine the memorization state of the memory cell.
The operation of reading of the threshold voltage value is equivalent to the operation of verification of the threshold voltage value and therefore the time for the reading of the stored datum coincides with the time for the verification of the stored datum.
It is thus evident that the faster the operation of verification will be, the quicker it will be possible to program the cell.
SUMMARY OF THE INVENTION
An embodiment of the present invention carries out the operation of in-writing verification of the threshold voltage value in a fraction of the reading time.
The embodiment includes a method for the in-writing verification of the threshold value of multilevel cells suitable to memorize n bits each, that provides for the use of a sense amplifier (detection amplifier). The sense amplifier includes a register with n bits, a generator of a reference current that varies as a function of the datum contained in the register, and a circuit for comparing the reference current produced by the current generator and the current that flows in a selected memory cell. The method includes: (a) loading the datum desired to be programmed in the selected memory cell in the register; (b) applying a programming pulse; (c) comparing the reference current corresponding to the datum and the current that flows in the cell: and repeating steps (b), (c) until it is verified that the current of the cell is lower than said reference current.
The value that the current in the memory cell has at the end of the programming operation is already known beforehand.
In the case under examination this can be used advantageously by memorizing the n bits to be written in the memory cell in a register, in such a way that the comparison between the current that flows from the flash cell and the known and constant one at the output of a digital analog conversion device is possible. For each operation of reading, therefore, n cycles of comparison are employed, and if the number of cells to be read is high, this operation involves a considerable expenditure of time.
The operation of verification works differently from the operation of reading: the value of the register in which the data to be written in the memory cell are memorized does never modify, while it is the current in the flash memory cells after each programming pulse that changes. It is possible to deduce, therefore, that for each operation of verification only one cycle of comparison is necessary and this brings about a reduction in verification time.
Owing to the present invention it is possible to realize a method for the programming and verification of multilevel non-volatile cells that is quicker, less expensive in terms of energy, less bulky as regards the traditional methods.
REFERENCES:
patent: 5701265 (1997-12-01), Calligaro et al.
patent: 5917753 (1999-06-01), Dallabora et al.
patent: 5930167 (1999-07-01), Lee et al.
Guaitini Giovanni
Pasotti Marco
Rolandi Pier Luigi
Galanthay Theodore E.
Iannucci Robert
Lam David
Nelms David
Seed IP Law Group PLLC
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