Input buffer circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C327S065000, C327S563000, C327S052000, C330S253000, C330S051000

Reexamination Certificate

active

06215339

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an input buffer circuit for receiving digital data signals from a transmission line according to the preamble of claim
1
. An input buffer circuit of this kind is known from EP-A-0 504 060.
Digital circuits and technology are the key for systems with an ever increasing performance and functionality. This goes together with a continuously increasing scale of integration and an increase in the complexity of digital systems. Different sections of such systems communicate via impedance matched transmission lines which constitute an inexpensive and convenient means for carrying data rates in the order of several hundred Mbit/s over short and medium distances within a digital system.
In complex systems, power consumption is a major point of concern. The more complex and compact the system, the more important it is that each system component uses as little operating power as possible. Differential signalling with low signalling voltages is well suited to meet the requirement of low power transmission and, due to the symmetric nature, also the requirement of noise immunity.
In order to transmit data via a symmetrical transmission line, a line driver circuit is required at the transmitting side of the transmission line in order to provide low impedance data signals. The amplitude of these data signals is low, in order to keep the power transmitted over the transmission line with a given characteristic impedance, reasonably small. At the receiver side of the transmission line an input buffer circuit is provided, for receiving the digital data signals and for outputting a corresponding digital signal to subsequent sections.
In large systems, e.g. if standardized interfaces between system subsections are provided, the number of available channels is sometimes higher than the number of actually needed channels. Regardless, whether an available channel is used or not, for each available channel an input buffer circuit is provided which will consume operating power. Of course, each input buffer could be individually connected to the power supply or disconnected from the power supply. This, however, would require special elements like jumpers or switches for allowing individual settings. Additional space would be required and the overall system reliability would be lower, and additional costs would arise in the process of manufacture.
It is, therefore, an object of the present invention to provide an input buffer circuit for receiving digital data signals from a transmission line, wherein the circuit is very power efficient even if it is not currently being used in a specific system configuration.
SUMMARY OF THE INVENTION
According to the present invention, this object is solved as defined in claim
1
.
Advantageous embodiments of the present invention are defined in the dependent claims.
The input buffer circuit according to the present invention monitors, whether data signals are present at its inputs. If data are detected, the input buffer circuit is switched into an operating state in order to receive the transmitted data and output the same. If no data are detected at the input of the buffer circuit, at least the portions not required for monitoring the presence of absence of input data and significantly contributing to the overall power consumption of the input buffer circuit, are switched into a standby mode with reduced power consumption or no power consumption at all. Preferably, means are provided for applying a predetermined potential to the output terminal of the input buffer circuit when in the standby state, in order to avoid unpredictable or undefined states in the subsequent digital circuitry.
Monitoring of the presence or absence of data at the input of the buffer circuit takes place by means of monitoring the signal amplitude across the inputs of the amplifier section. If an absolute voltage difference across the input terminals is above a predetermined threshold, this is an indication for data being present at the inputs. If, on the other hand, this absolute voltage difference is below the predetermined threshold, it indicates that no data are present at the inputs and that the input buffer circuit may switch into the standby state. The monitor section comprises an analogue multiplier circuit having first and second differential inputs and an output, as defined in claim
1
.
According to a preferred embodiment of the invention the operating or standby mode of the input buffer circuit is controlled by the output buffer connected to the transmitting side of the transmission line. If temporarily there are no data for the output buffer to be transmitted, the output buffer sets its outputs to equal potential, e.g. by means of switching off the power supply to the output buffer or by means of switching the outputs of the output buffer into a high impedance mode or disconnecting the outputs from the transmission line or by means of applying equal potential to the output terminals of the output buffer. At the receiving end of the transmission line, the input buffer will then switch into the low power standby mode, without the need to provide a separate signalling channel for power control.


REFERENCES:
patent: 3956643 (1976-05-01), Hite
patent: 4617473 (1986-10-01), Bingham
patent: 5003578 (1991-03-01), Lin
patent: 5412688 (1995-05-01), Marbot
patent: 5510751 (1996-04-01), Nauta
patent: 5606281 (1997-02-01), Gloaguen
patent: 5608352 (1997-03-01), Itakura
patent: 5703518 (1997-12-01), Yamamoto
patent: 5905408 (1999-05-01), Huijser
patent: 5991182 (1999-11-01), Novac et al.
patent: 4241215 (1994-06-01), None
patent: 0504060 (1992-09-01), None
patent: 0647898 (1995-04-01), None
Patent Abstract of Japan, Publication No. 03278741, Dec. 10, 1991.
Siemens “1 hr Programm,” Bestell Nr. A 19100-5 52-M 153, Aug. 26, 1994.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Input buffer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Input buffer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input buffer circuit will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2478038

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.