Non-volatile semiconductor memory device with block erase...

Details Non-volatile semiconductor memory device with block erase... Non-volatile semiconductor memory device with block erase...

1998-04-06

2001-05-29

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185270, C365S185110

Reexamination Certificate

active

06240022

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device which consists of memory cell units, such as NAND cells, AND cells, DINOR cells, etc., each formed of a plurality of memory cells connected to each other.
2. Description of the Related Art
An electrically erasable programmable EEPROM is known as a conventional non-volatile semiconductor memory device. In particular, attention has been paid to a NAND-cell type EEPROM consisting of a plurality of EEPROMs connected in series, since it is suitable to high integration.
Each memory cell (i.e. EEPROM) included in the NAND-cell type EEPROM has a FETMOS structure wherein a floating gate (a charged layer) and a control gate are provided on a semiconductor substrate with an insulating film interposed therebetween. Each NAND cell is constituted by a plurality of memory cells connected in series to each other. Each adjacent pair of the memory cells commonly use a single source and a single drain. A memory cell array is constituted by a plurality of NAND cells constructed as above and arranged in the form of a matrix.
The drains of NAND cells arranged in columns in the memory cell array are each located at an end of a corresponding NAND cell, and are commonly connected to a corresponding bit line via a corresponding selective gate transistor. On the other hand, the sources of the NAND cells arranged in columns are each located at the other end of a corresponding NAND cell, and are commonly connected to a common source line. The control gate of each memory transistor is connected to a corresponding one of control gate (word) lines arranged in rows in the memory cell array. The gate electrode of each selective gate transistor is connected to a corresponding one of selective gate lines arranged in rows in the memory cell array.
FIG. 7
is a plan view, showing a basic structure of each NAND cell formed of EEPROMs, while
FIGS. 8A and 8B
are sectional views, showing the structure.
FIG. 9
shows a circuit equivalent to the NAND cell shown in FIG.
7
. In this example, the NAND cell is constituted by connecting, in series, four memory cells M
1
-M
4
, two selective MOS transistors S
1
and S
2
, and its source and drain diffusion layers. A plurality of NAND cells constructed as above constitute a memory cell array.
The drain of the memory cell M
1
is connected to a bit line BL via a selective line S
1
. The source of the memory cell M
4
is connected to a source line via a selective transistor S
2
. The control gates
6
1
-
6
4
(CG
1
-CG
4
) of the memory cells M
1
-M
4
are connected to a word line WL which intersects the bit line BL. Although in this case, each NAND cell consists of four memory cells, it can be formed of a number 2
n
of memory cells.
The cell structure will be explained in more detail with reference to
FIGS. 8A and 8B
. An n-well
11
is formed on a p-type silicon substrate
10
, and a p-well
12
is formed on the n-well
11
. Memory cells are formed on the p-well
12
, and a peripheral circuit is provided in a region of the p-well other than the region of the same in which the memory cells are provided. The region in which the NAND cell is formed is defined by an element-separating insulation film
13
.
Each memory cell comprises a first gate insulation film
3
1
consisting of a thermally oxidized film with a thickness of 5-20 nm formed on the p-well
12
; a floating gate
4
(
4
1
,
4
2
,
4
3
,
4
4
) consisting of a first polycrystal silicon film with a thickness of 50-400 nm formed on the first gate insulation film 3
1
; a second gate insulation film
5
consisting of a thermally oxidized film with a thickness of 15-40 nm formed on the floating gate
4
; and a control gate
6
(
6
1
,
6
2
,
6
3
,
6
4
) consisting of a second polycrystal silicon film with a thickness of 100-400 nm formed on the second gate insulation film
5
. The control gates
6
are continuously arranged in one direction and serve as a single word line WL.
An n-type layer
9
which serves as a source/drain diffusion layer is commonly used by each adjacent pair of the memory cells. The drain of the NAND cell, which is located at an end thereof, is connected to a bit line
8
via the selective MOS transistor S
1
formed of a gate electrode
4
5
. The source of the NAND cell, which is located at the other end thereof, is grounded via the selective transistor S
2
formed of the gate electrode
4
6
.
The two selective transistors S
1
and S
2
are provided by respectively forming, on the p-well
12
, selective gates
4
(
4
5
,
4
6
) consisting of the first polycrystal silicon film, with a third gate insulation film
32
consisting of a thermal oxide film with a thickness of 25-40 nm interposed therebetween. On the selective gates
4
(
4
5
,
4
6
), the lines
6
(
6
5
,
6
6
) consisting of the second polycrystal silicon film are provided, with the second gate insulation film
5
interposed therebetween. The selective gates
4
5
and
4
6
are connected to the lines
6
5
,
6
6
, respectively, via through holes (not shown) formed at regular intervals, thereby reducing the resistance of each line.
The floating gates
4
1
-
4
4
, the control gates
6
1
-
6
4
, the selective gates
4
5
and
4
6
, and the lines
6
5
and
6
6
formed on the selective gates of all memory cells are simultaneously patterned using a single etching mask in the direction of channel length, thereby aligning the edges of the memory cells. The n-type layer
9
which serves as the source/drain diffusion layer is formed by injecting arsenic or phosphorus ions using, as masks, the control gates
6
1
-
6
4
and the wires
6
5
and
6
6
on the selective gates.
In the above-described structure, the coupling capacity C
1
between the floating gate
4
of each memory cell and the substrate
10
is set smaller than the coupling capacity C
2
between the floating gate
4
and the control gate
6
of each memory cell. This will be explained using specific cell parameters. In accordance with the rule of a pattern size of 0.6 &mgr;m, the floating gate and the control gate each have a width of 0.6 &mgr;m, and those opposite end portions of each floating gate
4
which have a length of 0.6 &mgr;m are provided on each adjacent pair of element-separating insulation films
13
. Further, the first gate insulation film
3
1
is formed of a thermal oxide film with a thickness of e.g. 10 nm, and the second insulation film
5
is formed of a thermal oxide film with a thickness of e.g. 28 nm. In this case, the following equations are established:
C
1
=&egr;/0.01
C
2
=3&egr;/0.028
where &egr; represents the dielectric constant of each thermal oxide film.
Accordingly, C
1
is smaller than C
2
.
FIG. 10
shows a circuit using a NAND cell. The following table 1 shows the relationship between the potentials of the gates, for explaining the erase, write and read operations of the circuit shown in FIG.
10
.
TABLE 1
FLASH
SELECTIVE WRITE
READ
ERASE
(M
4
)
(M
4
)
BL1
V
PP
′
0V
1-5V
BL2
V
PP
′
V
CC
0V
SOURCE
V
PP
′
0V
0V
SG1
V
PP
′
V
CC
V
CC
SG2
V
PP
′
0V
V
CC
CG1
0V
1/2 V
PP
V
CC
CG2
0V
1/2 V
PP
V
CC
CG3
0V
1/2 V
PP
V
CC
CG4
0V
V
PP
0V
P WELL
V
PP
′
0V
0V
N WELL
V
PP
′
0V
0V
First, an explanation will be given of flash erasion of data stored in all memory cells of the NAND cell (“flash erasion” means to erase all data at a time). In this example, the control gates CG
1
-CG
4
of all memory cells of each NAND cell are set at 0 V, the gates SG
1
and SG
2
of the selective MOS transistors S
11
and S
21
, the n-well
11
and the p-well
12
which surrounds the memory cells at “H” level (e.g. at a booster voltage Vpp
1
=18 V), and the bit lines BL
1
and BL
2
at Vpp
1
, too. As a result, an electric field occurs between the control gates of all memory cells and the p-well
12
, and electrons flow from the floating gates
4
of the memory cells to the p-well
12
because of a tunnel effect. The erase operation shifts the threshold voltage of all memory cells M
1
-M
4
to a

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