Low power multiplier for CPU and DSP

Details Low power multiplier for CPU and DSP Low power multiplier for CPU and DSP

1999-11-02

2001-08-14

Mai, Tan V. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S490000

Reexamination Certificate

active

06275842

ABSTRACT:

TECHNICAL FIELD
This invention relates to the processors, and more particularly, to multipliers for use in central processing units and digital signal processors.
BACKGROUND OF THE INVENTION
Hardware-based multipliers are often added to digital signal processors (DSP) and central processing units (CPU) to speed up the multiplication function, and thus speed up application execution. Typically, in DSPs and CPUs, the operands are loaded into respective registers, and are then supplied to the execution unit to have the appropriate operation performed. The execution unit is often made up of one or more function units, each of which has access to the operands stored in the registers, and which performed a particular dedicated function, e.g., add, Boolean arithmetic, or multiplication. The longest time taken by any of the function units represents the critical path of the execution unit, and determines the maximum speed of the execution unit. Since all the function units have access to the operands in parallel, all the function units perform their respective function each cycle of the execution unit. However, only the result from the function unit specified by the instruction currently being executed is supplied as the output of the execution unit. As a result, much work is performed, and power is consumed so doing, although only a small fraction of that consumed power contributes to the production of a beneficial result. In particular, the multiplier function unit, consumes the lion's share of the power, while it is often used only a small percentage of the time.
Known approaches to reducing the power used by the multiplier is to logically gate one or more of its inputs with a control signal that is responsive to the instruction type, where inputs are supplied to the multiplier only when multiplication is actually being performed. The most commonly used type of multiplier makes use of Booth encoding of one of the operands. It is known that gating the Booth encoded input yields the lowest power consumption in the multiplier. In addition, it is also well known that the critical path of the multiplier is along the path through the Booth encoder. As a result, disadvantageously, gating this input would add delay to the multiplier, and hence slow down the speed of the entire execution unit.
SUMMARY OF THE INVENTION
I have recognized that by gating the NEG output of the Booth encoding circuit and the multiplicand input that switching activity in the multiplier is minimized yet no delay is added to the multiplier's critical path. Advantageously, power consumption in the multiplier is significantly reduced, e.g., on the order of 90%, when multiplication is in fact not being performed. Additionally, by changing the structure of the last XOR gate of the partial product generation circuit, the need to gate the multiplicand input can be eliminated. Advantageously, this eliminates the extra circuitry which would otherwise be required to gate the multiplicand input, thus reducing cost. Furthermore, additional power savings may be achieved by efficiently resynchronizing the multiplicand input with the Booth encoded input to the partial product circuit.


REFERENCES:
patent: 5260898 (1993-11-01), Richardson
patent: 5262973 (1993-11-01), Richardson
patent: 9-101877 (1997-04-01), None
Patent Abstracts of Japan, vol. 097, No. 008, Aug. 29, 1997.
Weste, Neil H.E. and Eshraghian, Kamran, Principles of CMOS VLSI Design: A Systems Perspective, 2nded., 1993, Addison-Wesley Publishing Company, pps. 291-292; pps. 304-305 and pps. 547-555.

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