Semiconductor device with internal clock generating circuit...

Details Semiconductor device with internal clock generating circuit... Semiconductor device with internal clock generating circuit...

2000-03-08

2001-04-10

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S236000, C365S189050, C365S193000, C365S194000, C365S195000, C327S155000, C327S160000, C327S161000, C327S162000, C327S163000, C327S141000

Reexamination Certificate

active

06215726

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device performing data output in synchronization with a clock signal, and particularly to a semiconductor device generating an internal clock signal for control of data output using a delayed locked loop (DLL).
2. Description of the Background Art
With recent speeding up of processing systems, high-speed data transfer between a memory and a processing device such as a processor is realized by data transfer in synchronization with a clock signal. In data reading, the processing device samples data supplied in synchronization with the clock signal. As the clock signal is sped up, however, a data valid period is shortened correspondingly, which results in extremely stringent specification for timing of data input/output. To output data accurately in synchronization with such a clock signal, a clock synchronization circuit is provided within the memory to generate an internal clock signal in synchronization with an external clock signal for use in the data input/output. Here, a delayed locked loop (DLL) circuit is used to generate such an internal clock.
FIG. 18
is a diagram schematically showing a configuration of a main portion of a conventional semiconductor device incorporating an internal clock generating circuit. The semiconductor device
1
shown in
FIG. 18
includes: an input buffer
11
for buffering an external clock signal Ext.CLK to generate an internal clock signal CLKIN; a DLL circuit
10
for generating an outputting internal clock signal CLKO in synchronization with external clock signal Ext.CLK; a data output circuit
20
for transferring data DATA transferred from an internal circuit (not shown) according to outputting clock signal CLKO from DLL circuit
10
; and an output buffer
22
for buffering data transferred from data output circuit
20
for output as external data DOUT.
DLL circuit
10
includes: a variable delay line
12
for delaying internal clock signal CLKIN from input buffer
11
to generate outputting internal clock signal CLKO; an I/O replica circuit
13
for delaying outputting internal clock signal CLKO from variable delay line
12
by a prescribed time; a phase comparator
14
for comparing phases of a clock signal Int.CLK from I/O replica circuit
13
and internal clock signal CLKIN from input buffer
11
; an up/down counter
15
for performing a counting operation according to an up designating signal UP and a down designating signal DOWN from phase comparator
14
; and a decoder
16
for decoding a count value of up/down counter
15
to determine a delay amount of variable delay line
12
.
I/O replica circuit
13
adds to outputting internal clock signal CLKO, a delay time that is equivalent to a sum of delay times of input buffer
11
and output buffer
22
. Now, an operation of semiconductor device
1
shown in
FIG. 18
will be described with reference to a timing chart shown in FIG.
19
.
External clock signal Ext.CLK has a cycle time of tCK. With input buffer
11
having a delay time Di, internal clock signal CLKIN changes behind external clock signal Ext.CLK by delay time Di. I/O replica circuit
13
has a delay time Di+Do, which is the sum of delay time Di of input buffer
11
and a delay time Do of output buffer
22
. Phase comparator
14
compares the phase of internal clock signal Int.CLK from I/O replica circuit
13
and the phase of internal clock signal CLKIN from input buffer
11
and, according to the phase difference, activates up designating signal UP or down designating signal DOWN.
Up/down counter
15
increments/decrements its count value according to designating signals UP and DOWN from phase comparator
14
. Decoder
16
decodes the count value of up/down counter
15
, and sets the delay amount of variable delay line
12
corresponding to the count value of up/down counter
15
. Repeating the above-described operations results in matching in phases of internal clock signals CLKIN and Int.CLK with each other in the accuracy of at most a unit amount of delay of variable delay. line
12
.
In the case where variable delay line
12
has a delay time Dd, outputting internal clock signal CLKO from variable delay line
12
changes with delay of Di+Dd relative to external clock signal Ext.CLK. In a data output mode, data output circuit
20
transfers internal data DATA in synchronization with this outputting internal clock signal CLKO. Output buffer
22
is activated in the data output mode, and generates and outputs external data DOUT from the data output from data output circuit
20
.
Internal clock signal Int.CLK from I/O replica circuit
13
changes behind outputting internal clock signal CLKO by time Do+Di. Data output circuit
20
transmits data in synchronization with outputting internal clock signal CLKO, and output buffer
22
outputs external data DOUT after delay time Do. Thus, external output data DOUT is output with delay time Do behind clock signal CLKO. In other words, external data DOUT changes behind external clock signal Ext.CLK after a lapse of Di+Dd+Do. This time Di+Dd+Do equals one cycle period of external clock signal Ext.CLK. External data DOUT is thus output in synchronization with the change of external clock signal Ext.CLK.
In the data output operation as shown in
FIG. 19
, data are output in synchronization with rising and falling edges of external clock signal Ext.CLK. That is, data are output in a double data rate (DDR) mode. Utilizing I/O replica circuit
13
enables external data DOUT to be output in phase-synchronization with external dock signal Ext.CLK, in the accuracy of at most a unit delay amount of variable delay line
12
.
The processor performs taking-in of data supplied in synchronization with a data strobe signal (not shown) that is applied in parallel with external data DOUT. Therefore, the data strobe signal and external data DOUT are both in synchronization with external clock signal Ext.CLK, and thus, the external processor can take in (sample) data accurately. It is thus possible to perform accurate data transmission utilizing a high-speed clock signal.
If data output is performed using an internal clock generating circuit such as a DLL circuit, the most important parameter that should be taken into careful consideration is an edge-to-edge jitter. The edge-to-edge jitter is a jitter of a data valid period (data valid window) relative to an edge of an external clock signal. In the case where a data strobe signal (that is in synchronization with outputting internal clock signal CLKO from the DLL circuit) has a delay time A relative to external clock signal Ext.CLK as shown in
FIG. 20
, for example, DLL circuit
10
shown in
FIG. 18
performs phase adjustment. If this phase adjusting operation is performed in a time period during which external clock signal Ext.CLK is at an H level (time tCH) and the phase of this data strobe or outputting internal clock signal CLKO leads by time B that of external clock signal Ext.CLK, then the valid window of output data D
1
becomes narrower by (A+B) than the time period tCH during which external clock signal Ext.CLK is at the H level. If the phase of this data strobe or outputting internal clock signal CLKO is not adjusted until the next edge of external clock signal Ext.CLK (i.e., if the delay amount of DLL circuit is not adjusted), then the data strobe rises earlier than external clock signal Ext.CLK by time B. Therefore, the edge-to-edge jitter in this case is (B−B=0), and the valid window width of data D
2
at this time falls in the time period during which external clock signal Ext.CLK is at an L level. In the case of external clock signal Ext.CLK with duty ratio of 50%, the valid window period of data D
2
becomes time tCH.
The processor performs data sampling by shifting the phase of the data strobe by 90°, for example. Therefore, if the valid window of output data is narrowed, it becomes difficult to secure adequate data set-up/hold time for this sampling period, which hinders accu

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