Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
1999-04-29
2001-07-24
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S686000, C257S723000, C257S730000, C257S777000, C257S676000, C257S783000, C257S685000, C257S784000, C257S724000
Reexamination Certificate
active
06265760
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a chip stack type semiconductor device in which a plurality of semiconductor chips are mounted on a lead frame by the high-degree integration technique, and a semiconductor device lead frame and a method of manufacturing the same.
For example, a chip stack type semiconductor device of this type is used when logic cells and memory cells are to be mounted to form a hybrid circuit, when a memory capacity is to be increased, and when a plurality of semiconductors having different manufacturing processes and materials are to be mounted.
A structure conventionally known as a chip stack type semiconductor device of this type will be described with reference to FIG.
8
. In this conventional semiconductor device
1
, first and second semiconductor chips
3
and
4
are respectively adhered to the upper and lower surfaces of a die pad
2
of a lead frame L/F with conductive adhesive portions
5
a
and
5
b
of a silver paste or the like. Bonding wires
7
and
8
for respectively connecting the chips
3
and
4
to inner leads
6
of the lead frame L/F are connected to the upper and lower surfaces, respectively, of the inner leads
6
. A resin-encapsulated package
9
encapsulates the chips
3
and
4
stacked on and adhered to the die pad
2
, the inner leads
6
of the lead frame, and the bonding wires
7
and
8
.
This conventional semiconductor device is manufactured in accordance with the following manufacturing method.
The conductive adhesive portion
5
a
of a silver paste or the like is formed on the surface of the die pad
2
of the lead frame L/F, and the first chip
3
is mounted on it. The lead frame L/F mounted with the first chip
3
is turned back. The conductive adhesive portion
5
b
of a silver paste or the like is formed on the lower surface of the die pad
2
, and the second chip
4
is mounted on it. The resultant structure is baked.
The second chip
4
and the lower surfaces of the inner leads
6
are connected to each other by bonding with the bonding wires
8
. After that, the lead frame L/F is turned over. The first chip
3
and the upper surfaces of the inner leads
6
are connected to each other by bonding with the bonding wires
7
. After that, resin encapsulation and following operation are performed. An explanation of resin encapsulation and the following operation will be omitted.
FIG. 9
shows a case wherein a semiconductor device
1
uses a TAB tape
10
. In
FIG. 9
, the TAB tape
10
is adhered to a portion of the surface of a die pad
2
, extending laterally from a first chip
3
, through an adhesive
11
.
Metal wires
12
on the surface of the TAB tape
10
and the first chip
3
are connected to each other by bonding with bonding wires
7
. The metal wires
12
of the TAB tape
10
are also connected to inner leads
6
by bonding with bonding wires
13
.
Even in the semiconductor device
1
having this structure, the first chip
3
and a second chip
4
on the upper and lower surfaces, respectively, of the die pad
2
are connected to the inner leads
6
from both the upper and lower sides by turning a lead frame L/F over during the manufacture.
In the semiconductor device
1
having the conventional structure described above, as shown in
FIGS. 8 and 9
, to connect the first chip
3
by bonding, the second chip
4
must be connected by bonding, then the lead frame L/F must be turned over, and after that, the first chip
3
must be connected by bonding. As the bonding step must be performed twice during the manufacturing process, the number of manufacturing steps and accordingly the cost are increased.
After bonding connection of the second chip
4
is completed, the lead frame L/F is turned over to connect the first chip
3
by bonding. Therefore, the bonding wires
7
,
8
, and
13
tend to deform easily during the manufacture. The semiconductor device
1
thus must be handled carefully, and the yield in the manufacture decreases. As described above, the manufacture requires turning the lead frame over and performing connection by bonding on the two surfaces of the lead frame. A conventionally used manufacturing apparatus cannot be used directly, but a special apparatus is needed.
In the structure shown in
FIG. 9
, the TAB tape
10
is used as an interconnection in a resin-encapsulated package
9
for connecting the first and second chips
3
and
4
. This increases the cost of the lead frame L/F.
For example, Japanese Patent Laid-Open No. 3-116860 discloses a chip stack type semiconductor device. In this semiconductor device, insulating adhesive tapes are adhered to both the upper and lower surfaces of a lead frame, and first and second chips having different sizes are placed on the upper and lower surfaces of the lead frame. The chips and the inner leads of the lead frame are connected to each other by wire bonding.
In the semiconductor device disclosed in this reference, when the respective chips are mounted on the upper and lower surfaces of the lead frame through insulating adhesive films, two expensive insulating adhesive films are required to increase the material cost. In this conventional structure, when the chips are mounted on the upper and lower surfaces of the lead frame through the insulating adhesive films, the thickness of the package is difficult to decrease in the presence of the two insulating adhesive films.
Japanese Patent Laid-Open No. 7-38050 discloses a semiconductor device manufactured by using an LOC (Lead On Chip)-structure lead frame having isolated inner leads for internal interconnection.
As shown in this reference, it is technically difficult to cut outwardly extending inner leads and insulating tapes simultaneously. In the lead frame used in this conventional structure, the insulating tapes to which the isolated inner leads for internal interconnection are adhered are supported by the outwardly extending inner leads. Therefore, design of the inner leads for internal interconnection is limited due to the space.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above situation, and has as its object to provide a semiconductor device in which, when semiconductor chips having different sizes are to be mounted on the die pad of a lead frame and the respective chips are to be connected to the inner leads of the lead frame by using bonding wires, the number of manufacturing steps is reduced, the manufacturing operability is improved, and the manufacturing cost is reduced, and a semiconductor device lead frame and a method of manufacturing the same.
In order to achieve the above object, according to the present invention, there is provided a semiconductor device in which semiconductor chips are mounted on two surfaces of a die pad, a lower one of the semiconductor chips having a portion projecting outward from an upper one of the semiconductor chips, and the semiconductor chips being connected to integrally molded external connection leads through wiring members, wherein the lower semiconductor chip having the outwardly projecting portion has, on a surface thereof on the same side as an upper surface of the upper semiconductor chip, pads to be connected to the external connection leads.
REFERENCES:
patent: 5012323 (1991-04-01), Farnworth
patent: 5299092 (1994-03-01), Yaguchi et al.
patent: 5471369 (1995-11-01), Honda et al.
patent: 5502289 (1996-03-01), Takiar et al.
patent: 5523608 (1996-06-01), Kitaoka et al.
patent: 5545922 (1996-08-01), Golwalkar et al.
patent: 5615475 (1997-04-01), Burns
patent: 5640044 (1997-06-01), Takehashi et al.
patent: 5646829 (1997-07-01), Sota
patent: 5677569 (1997-10-01), Choi et al.
patent: 5724233 (1998-03-01), Honda et al.
patent: 5757080 (1998-05-01), Sota
patent: 5793101 (1998-08-01), Kuhn
patent: 5793108 (1998-08-01), Nakanishi et al.
patent: 5814881 (1998-09-01), Alagaratnam et al.
patent: 5898220 (1999-04-01), Ball
patent: 6072243 (2000-06-01), Nakanishi
patent: 6104084 (2000-08-01), Ishio et al.
patent: 6118184 (2000-09-01), Ishio et al.
patent: 4-179264 (1992-06-01), None
patent: 5-283601 (199
Ichinose Michihiko
Inaba Takehito
Oyachi Kenji
Helfgott & Karas P.C.
NEC Corporation
Williams Alexander O.
LandOfFree
Semiconductor device, and semiconductor device with die pad... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, and semiconductor device with die pad..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device, and semiconductor device with die pad... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2477502