Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1993-11-30
2001-04-17
Najjar, Saleh (Department: 2758)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S440000, C708S670000, C708S710000, C712S200000
Reexamination Certificate
active
06219688
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application relates to improvements in the inventions disclosed in the following copending U.S. patent applications, all of which are assigned to Texas Instruments:
U.S. patent application Ser. No. 08/263,501 filed Jun. 21, 1994 entitled “MULTI-PROCESSOR WITH CROSSBAR LINK OF PROCESSORS AND MEMORIES AND METHOD OF OPERATION”now abandoned , a continuation of U.S. patent application Ser. No. 08/135,754 filed Oct. 12, 1993 and now abandoned, a continuation of U.S. patent application Ser. No. 07/933,865 filed Aug. 21, 1993 and now abandoned, a continuation of U.S. patent application Ser. No. 07/435,591 filed Nov. 17, 1989 and now abandoned;
U.S. Pat. No. 5,212,777, issued May 18, 1993, filed Nov. 17, 1989 and entitled “SIMD/MIMD RECONFIGURABLE MULTI-PROCESSOR AND METHOD OF OPERATION”;
U.S. patent application Ser. No. 08/264,111 filed Jun. 22, 1994 entitled “RECONFIGURABLE COMMUNICATIONS FOR MULTI-PROCESSOR AND METHOD OF OPERATION,” a continuation of U.S patent application Ser. No. 07/895,565 filed Jun. 5, 1992 and now abandoned; now U.S. Pat. No. 5,522,083 a continuation of U.S. patent application Ser. No. 07/437,856 filed Nov. 17, 1989 and now abandoned;
U.S. patent application Ser. No. 08/264,582 filed Jun. 22, 1994 entitled “REDUCED AREA OF CROSSBAR AND METHOD OF OPERATION”, a continuation of U.S. patent application Ser. No. 07/437,852 filed Nov. 17, 1989 and now abandoned;
U.S. patent application Ser. No. 08/032,530 filed Mar. 15, 1993 entitled “SYNCHRONIZED MIMD MULTI-PROCESSING SYSTEM AND METHOD OF OPERATION,” now U.S. Pat. No. 6,038,584 a continuation of U.S. patent application Ser. No. 07/437,853 filed Nov. 17, 1989 and now abandoned;
U.S. Pat. No. 5,197,140 issued Mar. 23, 1993 filed Nov. 17, 1989 and entitled “SLICED ADDRESSING MULTI-PROCESSOR AND METHOD OF OPERATION”;
U.S. Pat. No. 5,339,447 issued Aug. 16, 1994; filed Nov. 17, 1989 entitled “ONES COUNTING CIRCUIT, UTILIZING A MATRIX OF INTERCONNECTED HALF-ADDERS, FOR COUNTING THE NUMBER OF ONES IN A BINARY STRING OF IMAGE DATA”;
U.S. Pat. No. 5,239,654 issued Aug. 24, 1993 filed Nov. 17, 1989 and entitled “DUAL MODE SIMD/MIMD PROCESSOR PROVIDING REUSE OF MIMD INSTRUCTION MEMORIES AS DATA MEMORIES WHEN OPERATING IN SIMD MODE”;
U.S. patent application Ser. No. 07/911,562 filed Jun. 29, 1992 entitled “IMAGING COMPUTER AND METHOD OF OPERATION” now U.S. Pat. No. 5,410,649, a continuation of U.S. patent application Ser. No. 07/437,854 filed Nov. 17, 1989 and now abandoned; and
U.S. Pat. No. 5,226,125 issued Jul. 6, 1993 filed Nov. 17, 1989 and entitled “SWITCH MATRIX HAVING INTEGRATED CROSSPOINT LOGIC AND METHOD OF OPERATION”.
This application is also related to the following concurrently filed U.S. patent applications, which include the same disclosure:
U.S. patent application Ser. No. 08/160,229 “THREE INPUT ARITHMETIC LOGIC UNIT WITH BARREL ROTATOR” now U.S. Pat. No. 5,490,828;
U.S. patent application Ser. No. 08/158,742 “ARITHMETIC LOGIC UNIT HAVING PLURAL INDEPENDENT SECTIONS AND REGISTER STORING RESULTANT INDICATOR BIT FROM EVERY SECTION” U.S. Pat. No. 5,640,518;
U.S. patent application Ser. No. 08/160,118 “MEMORY STORE FROM A REGISTER PAIR CONDITIONAL” now U.S. Pat. No. 6,058,473;
U.S. patent application Ser. No. 08/324,323 “ITERATIVE DIVISION APPARATUS, SYSTEM AND METHOD FORMING PLURAL QUOTIENT BITS PER ITERATION” now U.S. Pat. No. 5,442,581 a continuation of U.S. patent application Ser. No. 08/160,115 concurrently filed with this application and now abandoned;
U.S. patent application Ser. No. 08/158,285 “THREE INPUT ARITHMETIC LOGIC UNIT FORMING MIXED ARITHMETIC AND BOOLEAN COMBINATIONS” now abandoned;
U.S. patent application Ser. No. 08/160/119 “METHOD, APPARATUS AND SYSTEM FORMING THE SUM OF DATA IN PLURAL EQUAL SECTIONS OF A SINGLE DATA WORD” now U.S. Pat. No. 6,016,538;
U.S. patent application Ser. No. 08/159,359 “HUFFMAN ENCODING METHOD, CIRCUITS AND SYSTEM EMPLOYING MOST SIGNIFICANT BIT CHANGE FOR SIZE DETECTION” now U.S. Pat. No. 5,512,896;
U.S. patent application Ser. No. 08/160,296 “HUFFMAN DECODING METHOD, CIRCUIT AND SYSTEM EMPLOYING CONDITIONAL SUBTRACTION FOR CONVERSION OF NEGATIVE NUMBERS” now U.S. Pat. No. 5,479,166;
U.S. patent application Ser. No. 08/160,120 “ITERATIVE DIVISION APPARATUS, SYSTEM AND METHOD EMPLOYING LEFT MOST ONE'S DETECTION AND LEFT MOST ONE'S DETECTION WITH EXCLUSIVE OR” now U.S. Pat. No. 5,644,524;
U.S. patent application Ser. No. 08/160,114 “ADDRESS GENERATOR EMPLOYING SELECTIVE MERGE OF TWO INDEPENDENT ADDRESSES” now U.S. Pat. No. 5,712,999;
U.S. patent application Ser. No. 08/160,116 “METHOD, APPARATUS AND SYSTEM METHOD FOR CORRELATION”;
U.S. patent application Ser. No. 08/160,297 “LONG INSTRUCTION WORD CONTROLLING PLURAL INDEPENDENT PROCESSOR OPERATIONS” now U.S. Pat. No. 5,509,129;
U.S. patent application Ser. No. 08/159,346 “ROTATION REGISTER FOR ORTHOGONAL DATA TRANSFORMATION” now U.S. Pat. No. 6,067,615;
U.S. patent application Ser. No. 08/159,652 “MEDIAN FILTER METHOD, CIRCUIT AND SYSTEM” now abandoned;
U.S. patent application Ser. No. 08/159,344 “ARITHMETIC LOGIC UNIT WITH CONDITIONAL REGISTER SOURCE SELECTION” now U.S. Pat. No. 5,805,913;
U.S. patent application Ser. No. 08/160,301 “APPARATUS, SYSTEM AND METHOD FOR DIVISION BY ITERATION”
U.S. patent application Ser. No. 08/159,650 “MULTIPLY ROUNDING USING REDUNDANT CODED MULTIPLY RESULT” now U.S. Pat. No. 5,644,522;
U.S. patent application Ser. No. 08/159,349 “SPLIT MULTIPLY OPERATION” now U.S. Pat. No. 5,446,651;
U.S. patent application Ser. No. 08/158,741 “MIXED CONDITION TEST CONDITIONAL AND BRANCH OPERATIONS INCLUDING CONDITIONAL TEST FOR ZERO” now abandoned;
U.S. patent application Ser. No. 08/160,302 “PACKED WORD PAIR MULTIPLY OPERATION” now abandoned;
U.S. patent application Ser. No. 08/160,573 “THREE INPUT ARITHMETIC LOGIC UNIT WITH SHIFTER” now U.S. Pat. No. 6,098,163
U.S. patent application Ser. No. 08/159,282 “THREE INPUT ARITHMETIC LOGIC UNIT WITH MASK GENERATOR” now U.S. Pat. No. 5,590,350;
U.S. patent application Ser. No. 08/160,111 “THREE INPUT ARITHMETIC LOGIC UNIT WITH BARREL ROTATOR AND MASK GENERATOR” now U.S. Pat. No. 5,961,635;
U.S. patent application Ser. No. 08/160,298 “THREE INPUT ARITHMETIC LOGIC UNIT WITH SHIFTER AND MASK GENERATOR” now U.S. Pat. No. 5,974,539;
U.S. patent application Ser. No. 08/159,345 “THREE INPUT ARITHMETIC LOGIC UNIT FORMING THE SUM OF A FIRST INPUT ADDED WITH A FIRST BOOLEAN COMBINATION OF A SECOND INPUT AND THIRD INPUT PLUS A SECOND BOOLEAN COMBINATION OF THE SECOND AND THIRD INPUTS” now U.S. Pat. No. 5,485,411;
U.S. patent application Ser. No. 08/160,113 “THREE INPUT ARITHMETIC LOGIC UNIT FORMING THE SUM OF FIRST BOOLEAN COMBINATION OF FIRST, SECOND AND THIRD INPUTS PLUS A SECOND BOOLEAN COMBINATION OF FIRST, SECOND AND THIRD INPUTS” now U.S. Pat. No. 5,465,224;
U.S. patent application Ser. No. 08/159,640 “THREE INPUT ARITHMETIC LOGIC UNIT EMPLOYING CARRY PROPAGATE LOGIC” now abandoned; and
U.S. patent application Ser. No. 08/160,300 “DATA PROCESSING APPARATUS, SYSTEM AND METHOD FOR IF, THEN, ELSE OPERATION USING WRITE PRIORITY” now U.S. Pat. No. 6,026,484.
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is the field of digital data processing and more particularly microprocessor circuits, architectures and methods for digital data processing especially digital image/graphics processing.
BACKGROUND OF THE INVENTION
This invention relates to the field of computer graphics and in particular to bit mapped graphics. In bit mapped graphics computer memory stores data for each individual picture element or pixel of an image at memory locations that correspond to the location of that pixel within the image. This image may be an image to be displayed or a captured image to be manipulated, stored, displayed or retransmitted. The field of bit mapped computer graphics has benefited greatly from the lowered cost and increased capacity of dynamic random access memory (DRAM) and the lowered cost and increased processing power of microprocessors. These advantageous changes in the cost and performance of com
Guttag Karl M.
Read Christopher J.
Brady III W. James
Marshall, Jr. Robert D.
Najjar Saleh
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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