Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-10-08
2001-03-27
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S296000, C438S359000, C438S427000
Reexamination Certificate
active
06207533
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit fabrication, and more specifically to a method for planarizing a layer of material in an integrated circuit.
BACKGROUND OF THE INVENTION
Polishing processes, and more specifically chemical-mechanical polishing processes, have been used in the semiconductor industry to prepare both single crystal substrates and silicon on insulator substrates. In addition, chemical-mechanical polishing processes have also been used to planarize various conductive and insulating layers subsequently deposited on these substrates, during the integrated circuit fabrication process. For example, chemical-mechanical polishing has been used to planarize interlevel dielectric layers that lie in between two different levels of metal interconnect. Planarizing the interlevel dielectric layer, prior to the formation of the next level of interconnect, is highly desirable because it allows the next level of interconnect to be subsequently patterned and etched without the formation of conductive metal stringers, which can electrically short adjacent metal lines, and without the formation of thinned or notched metal lines, which can adversely effect device reliability. Similarly, chemical-mechanical polishing has been used to planarize conductive materials, such as tungsten, copper, and aluminum, to form planar contact plugs, via plugs, and interconnects. In addition, chemical-mechanical polishing has also been used to form trench isolation. In this process, trenches are formed and then subsequently filled with a deposited dielectric layer, such as silicon dioxide. The dielectric layer is then polished back to form dielectric filled isolation trenches, which are nearly planar with the adjacent active regions. In addition to being planar, the resulting trench isolation is also desirable because it allows the space separating adjacent active regions to be minimized, and thus allows integrated circuits with high device packing densities to be fabricated.
Unfortunately, it is difficult to accurately and reproducibly polish semiconductor substrates, and the materials subsequently deposited on them. One of the main reasons for is that it is very difficult to accurately and reproducibly determine when a selected thickness of material has been removed by a given polishing process. As a result, the materials being polished may be either under-polished or over-polished. Both of these results may adversely effect the functionality of an integrated circuit. For example, if the interlevel dielectric layer lying between two levels of metal interconnect is over-polished, then its thickness may be insufficient to prevent the two levels of interconnect from being electrically shorted to one another. On the other hand, if the interlayer dielectric layer is under-polished, then its increased thickness may result in the formation of electrically open vias. Similarly, under-polishing and over-polishing may also adversely effect the trench isolation process, as well as metallization processes where a selected thickness of material is to be reproducibly removed by a polishing process. Moreover, operating conditions that effect the polishing rate, such as the roughness of the polishing surface, may also change during the polishing process. Therefore, the inability to accurately and reproducibly determine when a selected thickness of material has been removed by a given polishing process may be further compounded by polishing rates that vary with time.
Accordingly, a need exists for a polishing process that can accurately and reproducibly remove a selected thickness of material.
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Blum David S
Bowers Charles
Chartered Semiconductor Manufacturing Ltd.
Wagner , Murabito & Hao LLP
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