Logic emulation system

Details Logic emulation system Logic emulation system

2000-02-25

2001-08-28

Teska, Kevin J. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

Reexamination Certificate

active

06282503

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logic emulation system that uses a plurality of component parts on a printed-circuit board to implement equivalent operations of logic circuits in LSIs (large-scale integrated circuits) and computers, thereby emulating the logical operations of these logic circuits.
2. Description of the Related Art
Logic circuits in LSIs and computers are verified traditionally by resorting to logic simulation and through trial manufacture of LSI boards. Logic simulation involves, illustratively, the implementation of the operations of the target logic circuit by use of a computer. One disadvantage of such computer-based logic simulation is that, because the simulation setup operates at very low speeds compared with actual logic circuits, verification takes more time as the scope of the logic circuit in question increases. Where an LSI board is to be produced for trial, several weeks are often required to wire and arrange the LSIs on the board. Thus, it is practically impossible to produce such test setups repeatedly for verification purposes. For this reason, logic emulation for circumventing the above deficiencies of the prior art is drawing increased attention.
Logic emulation utilizes a plurality of component parts mounted on a printed-circuit board to implement equivalent operations of the logic circuits in LSIs and computers. The LSI board setup is operated at a speed close to that of the actual logic circuit for verification.
FIG. 2
shows a conventional logic emulation system.
In
FIG. 2
, design data
110
on the target LSI are input through a workstation
100
. In this example, the target LSI is assumed to comprise input/output pins
111
through
116
and gates
121
through
124
.
A compiler
130
reads LSI design data and generates therefrom LSI mapping data
140
and PGA (programmable chip array) connection data ISO. These two kinds of data are used to produce a programmable gate array (PGA1)
141
and a programmable gate array (PGA2)
142
for performing the equivalent operations of the LSI, and a programmable interconnect device (PID
1
)
151
for connecting the PGAs.
When the scope of the gates in the target LSI is small, one programmable chip may be sufficient for mapping the gates. However, gates of greater scopes are generally mapped into a plurality of programmable chips. In the example of
FIG. 2
, gates
121
and
122
are mapped into the programmable chip
141
, and gates
123
and
124
are mapped into the programmable chip
142
. In logic simulation, the programmable chips
141
and
142
as well as the programmable interconnect chip
151
are mounted on a printed-circuit board
160
. For verification, the mounted parts are operated at a speed close to that of the actual logic circuit.
The logic simulation of the above-described type is discussed illustratively in Nikkei Electronics (the Jun. 22 issue, 1992, No. 557, pp. 203-217).
Logic emulation is used not only for logic verification but also for determining the specifications of the target logic circuit. For example, if the logic circuit includes a cache memory, determining the optimum capacity of that memory is an important decision to make, because the greater the capacity of the cache memory, the higher the probability of the desired data residing in that memory. However, boosting the capacity of the cache memory entails one disadvantage: It takes longer to transfer necessary data from main memory to the cache memory if the latter does not have the required data. This means that the capacity of the cache memory needs to be determined optimally in view of the application in which the target logic circuit is to be used. Utilizing logic emulation allows the performance of the target logic circuit to be measured while its cache memory is being varied in capacity until an optimum cache memory capacity is obtained.
Against such a background, the above-described prior art has a major disadvantage: When logic simulation is used to verify the logic of a particular logic circuit or to determine its specifications, even a simple logical change requires modifying the original design data (net list) and, correspondingly, remapping, rearranging and rewiring the programmable chips on the printed-circuit board. This leads to increasing man-hours and longer periods required for developing logic circuits. The same disadvantage is also experienced illustratively in cases where the capacity of the cache memory and observation signals need to be changed.
Another disadvantage of the prior art is that, because of their slow operating speeds, rewritable programmable chips used as PGAs are not fit for logic circuit emulation at desired speeds.
Although
FIG. 2
shows an example in which the logic emulation system is composed of programmable chips, logic circuit emulation is also available by use of integrated circuits that are not programmable. The latter case, however, requires altering the connections between parts on the printed-circuit board since some parts on the printed-circuit board need to be added or removed, and/or wiring patterns need to be cut and jumper wires added where necessary. These steps also add to the growing man-hours.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a logic emulation system that makes it easy to implement simple logical changes, alterations of the cache memory capacity, and changes in observation signals for performance evaluation, whereby the efficiency of logic emulation is enhanced.
In carrying out the invention and according to one aspect thereof, a logic emulation system constructed according to the teachings of the present invention includes dividing means for dividing the design data on a logic circuit into LSI mapping data representing a plurality of small-scale circuits and PGA connection data for connecting the LSI mapping data. The LSI mapping data and the PGA connection data are mapped into programmable chips, thereby generating an equivalent circuit of the logical circuit. The invention further includes judging means for comparing the design data on the logic circuit having logical changes made thereto with the design data on the logic circuit prior to the logical changes, the latter design data having been generated from the LSI mapping data and from the PGA connection data. The judging means further judges whether it is feasible to implement the logically changed logic circuit by adding small-scale circuits and by changing the PGA connection data. Thus, if the implementation of the logically changed logic circuit is judged to be feasible, the dividing means generates the LSI mapping data on the added small-scale circuits as well as the changed PGA connection data while the data thus generated are mapped into programmable chips, thereby generating an equivalent circuit of the logically changed logic circuit.
In a preferred structure according to the invention, the logic emulation system includes means for generating the design data on the logic circuit in two portions, one portion comprising fixed logic blocks for which there is a low probability that changes in specifications will occur, the other portion comprising variable logic blocks for which there is a higher probability that changes in specifications will occur, wherein the design data on the variable logic blocks are mapped into programmable chips independently of the design data on the fixed logic blocks. The “higher probability” is considered to be substantially higher than the “low probability”, the “low probability” representing an expectation that no changes will occur, and the “higher probability” representing an expectation that changes may occur.
In another preferred structure according to the invention, the logic simulation system includes an observation device for observing input/output signals of the programmable chips, and storing means for storing observation signal data representing those input/output pins of the programmable chips which are to be connected to the observation device

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