Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1998-08-05
2001-03-06
Grant, William (Department: 2121)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S098000, C700S117000, C700S121000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06198978
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit designing method and, more particularly, to a semiconductor integrated circuit designing system which efficiently conducts arrangement and wiring of circuit blocks into which repeaters as a means of reducing a wire delay are inserted and a designing method thereof.
2. Description of the Related Art
Design for a semiconductor integrated circuit (LSI) costs much time for the work of changing arrangement of circuit blocks in order to reduce a wire delay. As LSIs are made larger in scale to make wiring more complicated, there happens more often everywhere on an LSI chip a case where change of arrangement of circuit blocks for the purpose of shortening a predetermined wire results in adversely having other wires elongated. As a result, enormous time will be required before optimum arrangement and wiring of circuit blocks are determined. Then, the longer the time required for designing an LSI is, the more the LSI costs.
Under these circumstances, means for solving the above-described problem has been conventionally proposed. One of the conventional techniques of this kind is disclosed, for example, in Japanese Patent Laying-Open (Kokai) No. Heisei 4-251961, entitled “System for Designing Circuit Block Arrangement by CAD”, which is a system including a theoretical delay calculation unit for calculating a logical delay value of a target circuit based on logic connection information and circuit rules, a critical path decision unit for deciding on a critical path by the comparison between a logical delay value and predetermined constraint conditions of the target circuit, and a block arrangement unit for arranging a circuit block constituting a critical path so as to have a wire delay not more than a limiting value indicated in the circuit constraint conditions, as well as arranging a circuit block not constituting the critical path so as to make wiring easy, thereby deciding a critical path, with arrangement of circuit blocks changed so as to have as few long wires as possible.
The technique recited in the above literature, however, fails to take into consideration a method of inserting a repeater which is a common method for reducing a wire delay.
While insertion of a repeater into a long wire enables reduction of a delay caused by wire, it should ensure an area for arranging repeaters on an LSI chip. With repeaters included, therefore, layout of elements and wires should be further modified, which results in increase in an LSI designing time period.
Moreover, as reduction in scale of elements constituting an LSI and miniaturization of wires have been accelerated recently, a wire resistance and a wire capacitance are increased to make a wire length shorter into which repeaters are necessary to be inserted and a space between repeaters narrower, whereby the number of repeaters to be inserted tends to be sharply increased. This makes work for modifying layout of elements and wires more complicated to further increase an LSI designing time period.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an efficient semiconductor integrated circuit designing system which eliminates the above-described conventional shortcomings and enables reduction in time required for designing, as well as allowing drastic design change for the insertion of repeaters after detailed design to be avoided by obtaining, in LSI design, guidelines for repeater insertion prior to decision of detailed wiring, and a designing method thereof.
According to the first aspect of the invention, a semiconductor integrated circuit designing system which designs an LSI by arranging circuit blocks on an LSI chip and conducting wiring within the circuit blocks and between the circuit blocks, comprises
input means for receiving input of a technology parameter, a circuit parameter and a clock parameter regarding the circuit blocks constituting the LSI,
repeater information calculation means for obtaining information regarding insertion of repeaters by using the parameters applied through the input means,
circuit block arrangement means for arranging the circuit blocks based on the information regarding insertion of repeaters obtained by the repeater information calculation means,
delay calculation means for calculating a wire delay of wiring between the circuit blocks arranged by the circuit block arrangement means,
cycle time calculation means for obtaining a cycle time of the entire LSI based on a delay value calculated by the delay calculation means, and
detailed wiring means for conducting detailed wiring within the circuit blocks on the LSI whose arrangement on a circuit block basis and wiring processing have been completed.
In the preferred construction, the repeater information calculation means predicts,
as information regarding insertion of repeaters, at least a size and a wire length of a circuit block which will require repeater insertion.
In another preferred construction, the repeater information calculation means predicts,
as information regarding insertion of repeaters, at least
a size and a wire length of a circuit block which will require repeater insertion,
and a minimum necessary number of stages of repeaters inserted and a minimum necessary ratio of a gate width to a gate length of a repeater with respect to a wire which requires repeater insertion.
In another preferred construction, the repeater information calculation means predicts,
as information regarding insertion of repeaters, at least a block size of the circuit block where repeaters having a minimum necessary number of insertion stages and a minimum necessary ratio of a gate width to a gate length would be inserted into every wire which will require repeater insertion by using a wire distribution predicted from the parameters.
In another preferred construction, the repeater information calculation means predicts,
as information regarding insertion of repeaters, at least
a size and a wire length of a circuit block which will require repeater insertion,
a minimum necessary number of stages of repeaters inserted and a minimum necessary ratio of a gate width to a gate length of a repeater with respect to a wire which requires repeater insertion, and
a block size of the circuit block where repeaters having a minimum necessary number of insertion stages and a minimum necessary ratio of a gate width to a gate length would be inserted into every wire which will require repeater insertion by using a wire distribution predicted from the parameters.
In another preferred construction, the repeater information calculation means predicts,
as information regarding insertion of repeaters, at least a size and a wire length of a circuit block which will require repeater insertion, and
the circuit block arrangement means
limits a size of each circuit block to a size which will require no repeater insertion to arrange the circuit block.
In another preferred construction, the repeater information calculation means predicts,
as information regarding insertion of repeaters, at least
a size and a wire length of a circuit block which will require repeater insertion,
and a minimum necessary number of stages of repeaters inserted and a minimum necessary ratio of a gate width to a gate length of a repeater with respect to a wire which requires repeater insertion, and
the circuit block arrangement means
estimates an area necessary for the arrangement of the circuit blocks and wiring between the circuit blocks and prepares a region for wiring among the circuit blocks according to an obtained value to arrange the circuit blocks.
According to the second aspect of the invention, a semiconductor integrated circuit designing method of designing an LSI by arranging circuit blocks on an LSI chip and conducting wiring within the circuit blocks and between the circuit blocks, comprising the steps of
receiving input of a technology parameter, a circuit parameter and a clock parameter regarding the circuit blocks constituting the LSI,
obtaining info
Grant William
NEC Corporation
Patel Ramesh
Sughrue Mion Zinn Macpeak & Seas, PLLC
LandOfFree
Semiconductor integrated circuit designing system taking... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit designing system taking..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit designing system taking... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2473014