Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By pulse coincidence
Utility Patent
1998-11-04
2001-01-02
Nu Ton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By pulse coincidence
C327S589000
Utility Patent
active
06169423
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method and a circuit for regulating the duration of an ATD pulse synchronization signal for the read phase of non-volatile memory cells in electronic memory devices integrated in a semiconductor.
In particular, the invention relates to a circuit for regulating an ATD pulse synchronization signal in order to regulate the read phase of non-volatile memory cells in electronic memory devices integrated in a semiconductor, the circuit being of a type which is controlled by a change of logic state on at least one of a plurality of address input terminals of said memory cells, and comprises a NOR type of structure between said address terminals and an output node whence an equalization signal to a sense amplifier is derived.
BACKGROUND OF THE INVENTION
As is well known, the read mode, for reading the contents of the cells of a semiconductor integrated electronic memory circuit, is entered by completing a predetermined sequence of operations known as the reading cycle.
A reading cycle begins with the memory address of data to be read being presented to the input terminals of a memory circuit. An input stage senses the switching of an address presented to these terminals, thereby to initiate a reading operation.
Row and column decoding circuits will select the memory word that has been addressed.
The circuit portion arranged to read the contents of the memory cells and convert the analog data read to digital data is referred to as the sense or read amplifier. This amplifier usually is of the differential type and has a pair of inputs which are connected to a cell of the memory matrix and a reference cell, respectively. Reading is enabled by an unbalance in the loads of the matrix leg and the reference leg.
The data sensed by the sense amplifier is then output through a buffer output stage.
Each of the above phases of the reading cycle must have a preset duration consistent with the memory access times specified by the memory circuit specifications.
All of the various phases of the reading cycle are clocked by synchronization pulses derived from a single main or ATD (Address Transition Detection) pulse. The ATD pulse is generated within the memory circuit whenever a change in address is detected on the input terminals.
In general, the ATD pulse is generated by a NOR structure whose output is at a normally high logic level.
Upon the occurrence of a change in logic level at even one only of the input terminals, the NOR structure switches its output to allow a terminal from which the ATD pulse is delivered to be discharged toward ground.
Shown schematically in the accompanying
FIG. 1
is circuitry for generating the ATD signal according to the prior art.
FIG. 1
shows an ATD cell or circuitry
11
comprising two N-channel MOS input transistors, indicated at M
1
and M
2
, which are highly conductive on account of their high W/L ratio.
The cell
1
further comprises a pair of inverters I
1
, I
2
, each including a CMOS complementary pair having a pull-up transistor and a pull-down transistor. The pull-up transistors of the inverters I
1
, I
2
are highly resistive, and therefore little conductive, they having a reduced W/L ratio.
The structure resulting from the coupling of the inverters I
1
and I
2
is that of a latch register
3
having outputs Q and {overscore (Q)}, wherein the former, Q, is at a normally high logic level.
The latch
3
is input a signal AX and the corresponding negated signal AX_N from one of said input terminals, as smoothed by capacitors C
1
and C
2
. These signals are enabled to pass on to the latch
3
by the respective NMOS transistors M
1
and M
2
.
During the wait phase, only one of the input signals will be at a high logic value, e.g., AX_N. The capacitor C
2
will be discharged by the pull-up of the first inverter I
1
.
Upon the occurrence of an input transition, the capacitor C
1
of the transistor M
1
is quickly discharged, while the capacitor C
2
begins to be charged by the pull-up of the second inverter I
2
. In consequence of this, the first output Q of the latch
3
is at once brought to a low logic level. The other output Q# will instead take a little longer to change its state because the pull-up transistors of the inverters I
1
, I
2
are highly resistive. Thus, there will be a time period when both said outputs are at a low logic level.
With the outputs Q and {overscore (Q)} connected directly to the respective inputs of a logic gate I
3
of the NOR type, the output of the gate I
3
will be driven to a high logic level, thereby allowing an NMOS transistor M
3
connected to the output node
4
of the circuit
11
to be turned on.
Associated with each address input terminal of the memory circuit is a cell
11
, and a plurality of cells have their outputs tied to a common line as shown schematically in FIG.
2
.
In this approach, referred to in the art as the distributed NOR, the output
18
, for each cell, isconnected to a single ATD-LINE line
7
which is usually in the form of a metallization line taken to the supply Vdd through a PMOS transistor M
4
having its control terminal connected to a ground GND.
An ATD pulse is delivered from this line
7
through an inverter
5
.
Each ATD cell
11
can bias the line
7
to ground on the occurrence of an input transition. This line
7
being relatively long, it exhibits resistance and intrinsic capacitance of relatively high values, and if the switching involves all the addresses in parallel, the line
7
will be discharged at a very fast rate; otherwise, when the switching only affects the farthest terminal from the output node, the line
7
would be discharged at a slower rate.
The ATD signal performs two basic functions: a first is that of initiating the supply voltage boost operations, and the second is that of initiating the equalization of the sense amplifier nodes.
Shown schematically in the accompanying
FIG. 3
are the main features of a conventional sense amplifier.
A circuit block A represents that portion of the circuit which is intended for the current/voltage conversion, and a circuit block B represents the circuit portion which drives the output stages. The block A is to convert the value of the current, taken up by the non-volatile memory cells being written or erased, to a voltage.
The sense amplifier can discriminate between the logic contents, a “0” or a “1”, of a selected memory cell by verifying the unbalance of the matrix and reference nodes Vref and Vmat, respectively.
The conventional technique is to equalizing the nodes Vref and Vmat before effecting a reading.
The ATD signal is to generate an equalization signal, designated SAEQ hereinafter, to prepare the sense amplifier for a reading operation to be completed within the shortest possible time.
FIG. 4
is a plot vs. time of a plurality of voltage signals present in the memory circuit immediately after a transition on an address input.
A rise in the signal SAEQ reflects in a similar rise of the boost signal for the memory row or word line, and in a short phase of equalization of the nodes Vref and Vmat. The read phase proper takes place on the falling edge of the signal SAEQ, when the control of the nodes Vref and Vmat is shifted from the equalization network to the reference and the matrix cell.
From all of the above considerations, it can be appreciated that the duration of the pulse SAEQ is vital to the memory access time.
To avoid harmful oscillations of the nodes Vref and Vmat, the equalization network should only be released once the selected cell is biased at the highest gate voltage and, accordingly, able to take up maximum current. Otherwise, an erased cell could be mistaken for a written one.
In this respect, it should be considered that memories operated at low supply voltages require that the cell be biased with a boosted voltage.
Furthermore, in the prior art solutions, the ATD pulse is extended through a chain of inverters to provide the signal SAEQ; the consequent timing is highly responsive to temperature and supply voltage variations, and for modern memory device
Campardo Giovanni
Ferrario Donato
Micheloni Rino
Zammattio Matteo
Carlson, Esq. David V.
Galanthay, Esq. Theodore E.
Nu Ton My-Trang
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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