Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-11-15
2001-05-15
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S407000
Reexamination Certificate
active
06232824
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a structure of a semiconductor device having an internal potential generation circuit receiving an external power supply potential and generating an internal power supply potential.
Description of the Background Art
As a result of a rapidly growing popularity of portable information terminal equipment in recent years, storage element mounted on such equipment is required to operate for a long time by battery.
Mostly, a dynamic random access memory (hereinafter referred to as DRAM) is mounted as such storage element on portable information terminal equipment because of a low cost per bit. Data written in the DRAM is lost by degrees when abandoned. Therefore, an operation called “refresh operation” is necessary for holding data.
One way for reducing a current Iccsr consumed in the DRAM during the refresh operation is to optimize a design of a circuit portion where a current constantly flows and to reduce a through current constantly flowing through this circuit portion. Here, it is also preferable that a so-called standby current Iccs is reduced. For this purpose, again, the reduction of the constant through current as mentioned above is important. Hereinafter, an internal potential generation circuit generating an internal potential of a DRAM will be described as an example of such circuit where a constant current flows in the DRAM.
The internal potential generation circuit greatly contributes to the reduction of a current consumed during the operation of the DRAM because it supplies a predetermined lower potential than an external power supply voltage to internal circuitry of the DRAM. It is important to set an internal power supply potential Vdds output from the internal potential generation circuit at a lower level especially for the reduction of a current Iccsr consumed during the refresh operation.
FIG. 17
is a schematic block diagram referenced for describing a structure of a conventional internal potential generation circuit
8000
including a voltage conversion circuit
8040
for a sense amplifier for supplying internal power supply potential Vdds to a sense amplifier S/A of a DRAM.
The conventional internal potential generation circuit
8000
includes a constant current source
8010
receiving an external power supply potential Vcc and a ground potential Vss for operation and generating bias potentials VBH and VBL for defining an amount of a through current of internal potential generation circuit
8000
; a Vref generation circuit
8020
receiving external power supply potential Vcc and ground potential Vss for operation and generating a basic reference potential Vref for generating an internal power supply potential Vdds based on bias potential VBH; a buffer circuit
8030
receiving bias potential VBL and basic reference potential Vref and generating a reference potential VrefM for generating internal power supply potential Vdds; and a voltage conversion circuit
8040
receiving reference potential VrefM, activated by a signal QON and supplying internal power supply potential Vdds as an output.
In an example shown in
FIG. 17
, sense amplifier S/A is supplied with internal power supply potential Vdds via a p-channel MOS transistor TPO controlled by a signal ZSOP, and is supplied with ground potential Vss via an n-channel MOS transistor TNO controlled by a signal SON.
Sense amplifier S/A is connected to a plurality of memory cells MC via bit line pairs BL and /BL. In
FIG. 17
, only a single memory cell MC is shown to be connected to sense amplifier S/A via a bit line BL as an example. A precharge/equalize circuit
8100
for equalizing potential levels of paired bit lines BL and /BL in response to a signal BLEQ and for turning the potential levels to a precharge potential level is provided between paired bit lines BL and /BL.
Memory cell MC connected to bit line BL includes a memory cell transistor TM opening and closing according to a potential level of word line WL and a memory cell capacitor Cs having one end coupled to a cell plate potential Vcp and another end connectable to bit line BL via transistor TM. Here, in general, the cell plate potential takes a level half a potential corresponding to an “H” level data stored in the memory cell capacitor.
In the structure as shown in
FIG. 17
, the current consumed during operations can be reduced because internal power supply potential Vdds lower than the external power supply potential is supplied to sense amplifier S/A as described above.
However, as the level of internal power supply potential Vdds is low at the time of initiation of a sense operation, a gate-source potential Vgs of the transistor constituting sense amplifier S/A becomes low. This causes a delay of the sense operation by sense amplifier S/A.
In addition, with the decrease in chip area, a ratio (Cpb/Cb) of decoupling capacitance Cpb present on an interconnection between voltage conversion circuit
8040
and sense amplifier S/A to capacitance Cb charged and discharged to and from bit line BL and /BL at the sense operation tends to decrease. Before the initiation of the sense operation, capacitance Cpb holds the potential level of internal power supply potential Vdds. Under this condition, electrical charges are supplied from capacitance Cpb into charge/discharge capacitance Cb during a period from the start of the sense operation to the time voltage conversion circuit
8040
actually starts to supply internal power supply potential Vdds of a given level. Therefore, the decrease in capacitance ratio Cpb/Cb means increase in an amount of transient decrease of internal power supply potential Vdds supplied from the sense amplifier S/A compared with a desired level.
The larger transient decrease of internal power supply potential Vdds level means increase in delay of the sense operation as described above. Therefore, if a period where internal power supply potential Vdds transiently decreases is required to be shortened for the suppression of delay of sense operation, current supplying capability of internal potential generation circuit
8000
must be increased also in the transient period described above. This leads to a problem of increase in standby current of internal potential generation circuit
8000
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an internal potential generation circuit capable of suppressing a standby current value while suppressing a transient variation in level of an internal power supply potential supplied from an internal voltage down converting circuit.
In brief, the present invention is a semiconductor device including a reference potential generation circuit and an internal circuit.
The reference potential generation circuit receives an external power supply potential and selectively outputting one of a plurality of reference potentials according to an operation mode. The reference potential generation circuit includes a plurality of potential generation circuits each generating one of the plurality of reference potentials and increasing a current driving capability at least for a predetermined time period after the transition of the operation mode, and a switching circuit receiving outputs of the plurality of potential generation circuit and supplying one of the outputs through switching according to the operation mode. The internal circuit operates based on the output of the reference potential generation circuit.
Preferably, in the semiconductor device according to the present invention, the potential generation circuits each include a basic reference potential generation circuit generating a basic reference potential corresponding to the reference potential to be generated, and a buffer circuit supplying the reference potential as an output according to the basic reference potential. The buffer circuit includes an output node, a drive circuit receiving the external power supply potential and driving a potential level of the output node to the reference potential according to the basic reference potential, and
Kim Jung Ho
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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