Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2000-02-02
2001-05-22
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Resistor
Reexamination Certificate
active
06235602
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to an EEPROM (Electrically Erasable and Programmable ROM) which is a semiconductor storage device incorporating a boosting circuit.
A high voltage is required for write/erase of data for the cells of a semiconductor storage device such as an EEPROM. But, incorporating a boosting circuit in the device makes it unnecessary to provide a high voltage source externally. Thus, the voltage supplied from a certain external voltage source can be boosted to a minus or plus voltage. In this case, whether or not a desired potential has been generated can be decided by monitoring it using a detection circuit. For example, a conventional DINOR (Divided bit-line NOR) type flash memory, disclosed in 1992 IEDM TECHNICAL DIGEST pp. 599-602 “A NOVEL CELL STRUCTURE SUITABLE FOR A 3 VOLT OPERATION, SECTOR ERASE FLASH MEMORY” 1995 ISSCC DIGEST OF TECHNICAL PAPERS “A 3.3 v-Only 16 Mb DINOR flash Memory”, has a circuit configuration of boosting and detecting.
As shown in
FIG. 15
, the potentials generated form boosting circuits
1
a
and
1
b
are connected to a resistor
3
of the detection circuit
2
. The potential at a prescribed position of the flash memory
3
is detected by a detecting section
4
.
In the DINOR type flash memory, the potentials of 10 V and −8 V are generated by boosting circuits
1
a
and
1
b
from a single external power supply voltage (not shown). For example, assuming that the connecting points between the boosting circuits
1
a
,
1
b
and the resistor
3
are A and B, when the potential at the detecting point
4
provided at the point dividing the segment between A and B at a rate of 8.5:9.5 is 1.5 V, it is recognized that a desired potential has been generated.
The resistor
3
used in such a detecting circuit is made of the same material when the floating gate and control gate constituting a memory cell is fabricated.
In order to prevent the boosted potential in the boosting circuits
1
a
,
1
b
from being reduced, the detecting circuit
2
is required to suppress power consumption and prevent surplus current leak from the boosting circuits
1
a
,
1
b
. This requires that the resistance of the resistor
3
is relatively large so that the current value flowing the detecting circuit
2
is small.
However, since the resistor
3
used in the detection circuit
2
of the conventional EEPROM is made of the same as that of a floating gate or control gate, it is made of a polysilicon film or a polycide film, i.e, a laminated film composed of a polysilicon film and a refractory metal silicide film. For this reason, the floating gate made of a polysilicon film with a small sheet resistance, e.g. a thickness of 100 nm and boron impurity concentration of 7E20/cm
3
has a small sheet resistance of about 70 &OHgr;/
H
T
. The control gate made of a polyside film of a WSi film of 100 nm and a polysilicon film of 100 nm used as a word line of the memory cell has a very small sheet resistance of about 12 &OHgr;/
H
T
.
Thus, the resistor
3
, which is made of a material having a small sheet resistance, leads to an increase in the area for assuring resistance and hence is not suitable for requirement of miniaturization and high-integration in recent years.
In the resistor
3
made of the polysilicon of the floating gate, when the oxide film on the polysilicon film is etched for connection to the boosting circuits
1
a
,
1
b
and the detecting point to form a connecting hole, because of over-etching, the connecting hole might penetrate through the polysilicon as shown in FIG.
16
. In
FIG. 16
,
3
a denotes the polysilicon of the floating gate constituting the resistor
3
;
5
denotes a semiconductor substrate (hereinafter referred to as “substrate”);
6
denotes a field oxide film formed on the substrate
5
;
7
denotes an oxide film formed on the polysilicon film
3
a
;
8
denotes a connecting hole formed in the oxide film; and
9
denotes a wiring layer connected to the polysilicon film
3
a.
The polysilicon film
3
a
of the floating gate is a thin film having e.g. 100 nm or so, and is thin particularly on the field oxide film
6
because of the variation in the film thickness. Therefore, as shown in
FIG. 16
, when the connecting hole
8
is formed, because of over-etching, punch-through may easily occur in the polysilicon film
3
a
. The contact resistance with the wiring layer
9
to be formed in the subsequent step may increase. Further, since the underlying field oxide film
6
is easily etched, the hole may partially reach the underlying substrate
5
(not shown). In this case, the polysilicon film
3
a
and the substrate
5
may be shortcircuited.
SUMMARY OF THE INVENTION
In order to solve the above problem, in a semiconductor storage device incorporating a boosting circuit and a detecting circuit for detecting its potential, the present invention intends to provide a structure of a semiconductor device which can reduce the area of a resistor used in the detecting circuit to realize its miniaturization and high-integration and detect the potential in the boosting circuit with high reliability, and a method of fabricating it.
The semiconductor device of aspect
1
of the present invention incorporates, in a circuit configuration on a semiconductor substrate, a boosting circuit for boosting an external power supply voltage to a plus or minus voltage; and a detecting circuit having a resistor formed of an impurity diffused layer so that the plus voltage and the minus voltage boosted by the boosting circuit is connected to the resistor, respectively to detect a potential at a prescribed point thereby verifying if or not the boosting circuit has generated a desired potential.
A semiconductor device of aspect
2
according to aspect
1
defines a structure, wherein in the semiconductor substrate having a first conduction type, a well region having the first conduction type and another well region having a second conduction type are formed, and surrounding the lower surface and side of the first-conduction-type well region, and the impurity diffused layer constituting the resistor is formed to have the second conduction type within the well region having the first conduction type.
A semiconductor device of aspect
3
defines a structure, wherein the well region having the second conduction type is formed in the semiconductor substrate having the first conduction type, and the impurity diffused layer constituting the resistor is formed to have the first conduction type within the well region having the second conduction type.
A semiconductor device of aspect
4
defines a structure, wherein elements of an EEPROM (Electrically Erasable and Programmable ROM) are constituted on the semiconductor substrate, and the boosting circuit and the detecting circuit are included in the EEPROM.
A semiconductor device of aspect
5
defines a structure, wherein elements of a DINOR (Divided bit-line NOR) type flash memory are constituted on the semiconductor substrate, and the boosting circuit and the detecting circuit are included in the DINOR type flash memory.
A semiconductor device of aspect
6
defines a structure, wherein the plus boosted potential VH-by the boosting circuit is connected to the one end of the impurity diffused layer, and the minus boosted potential VL is connected to the other end of the impurity diffused layer; when the detecting circuit operates, a fixed potential Va is applied to the well region having the first conduction type, a fixed potential Vb is applied to the well region having the second conduction type and a fixed potential Vc is applied to the semiconductor substrate, and the fixed potentials Va, Vb and Vc are set so that at the respective junctions between the impurity diffused layer and the well region having the first conduction type, between the well regions having the first and second conduction types and between the well region having the second conduction type and the semiconductor substrate, and the potential difference between the region
Bowers Charles
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Thompson Craig
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