Method and apparatus for executing an instruction with multiple

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395800, 395581, 364DIG1, 364DIG2, G06F 108, G06F 938, G06F 942

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057375615

ABSTRACT:
A multi-alternative structure, such as a case instruction, in a computer system that can be executed in one cycle. The computer system of the present invention executes multiple instructions, wherein condition indicators are set according to the execution of each instruction. The multi-alternative structure includes conditional branching options, one of which being chosen according to the state of the condition indicators at the time the multi-alternative structure is executed. The method and apparatus includes registers for storing each of the target address. The registers are loaded prior to the execution of the multi-alternative structure, wherein upon execution, the chosen target address may be obtained quickly, such that the multi-alternative instruction is executed within one cycle.

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patent: 5203002 (1993-04-01), Wetzel

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