Multiple level flash memory

Details Multiple level flash memory Multiple level flash memory

2000-10-06

2001-08-14

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200, C365S185030, C365S189090

Reexamination Certificate

active

06275417

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed general to non-volatile memory including so-called multiple-level memory capable of storing more than one data-bit per cell, and more particularly to circuits and techniques for reading date from multiple-level non-volatile memory cells.
BACKGROUND OF THE INVENTION
Historically non-volatile memory such as electrically erasable programmable read-only-memory (EEPROM) or flash memory provided memory cells that were binary, and could store a single bit, e.g., a logical or binary “0” or “1”. A typical memory cell is a MOS device that includes source and drain regions formed in a substrate, a floating gate separated from the source, drain, and intermediate region of the substrate by a thin oxide layer, and an overlying control gate separated from the floating gate by a thicker oxide layer.
Coupling appropriate voltage levels to the control gate, source, or drain can cause electrons to collect on the floating gate, where their presence tends to counteract the voltage level on the floating gate, reducing source-drain current flow through the cell. A sense amplifier coupled to the source of the cell can detect the reduced current flow and report a “0” as being stored in the cell. On the other hand, when the cell is erased by coupling appropriate voltages to the control gate, source, or drain, the floating gate retains minimal charge and control gate potential will turn-on the cell, producing drain-source current flow that the sense amplifier reports as a stored “1”.
Discerning whether a memory cell is storing a “0” or “1” is straightforward. But more recently, in an attempt to increase storage density and low storage cost per bit, so-called multi-level EEPROM and flash memory units have been developed in which a memory cell can store more than one-bit of data. In essence the memory cell now stores what may be described as analog values and the multiple-level cell is characterized by an analog voltage threshold value, Vt. Although multi-level cells and arrays can provide density and cost advantages, it is more difficult to read and identify multiple values stored in a cell, than to read whether the cell is turned off (“0”) or on (“1”).
Assume a multi-level cell is to store one of sixteen levels. If the analog Vt distribution is from about 1.0 VDC to about 5.5 VDC, the &Dgr;Vt value associated with a given storage level is only 300 mV, e.g., (5.5-1.0)/15. Discerning which of the multiple levels has been stored requires accurately and preferably rapidly discerning between &Dgr;Vt values that are only 300 mV apart. The requirement to accurately sense with sufficient resolution of at least 300 mV over a range of about 1.0 VDC to about 5.5 VDC can be challenging in practice.
Several solutions have been directed to the problem of reading from multi-level memory cells. For example, U.S. Pat. No. 5,508,958 to Fazio, et al. (1996) and U.S. Pat. No. 5,751,635 to Wong, et al. (1998) disclose techniques for sensing the state of floating gate memory cells by applying a step-wise increasing variable voltage to the control gate of the memory cells.
FIG. 1
herein exemplifies this approach, in which a stepwise-increased voltage (or ramped voltage) is applied to the control gates of cells to alter the drain-source channel current (Ids)of the cells. The value of Ids will change stepwise, according to the difference between the nominal Vt value for the cell, and the control gate voltage at the moment.
In Fazio '958 and Wong '635 configurations, sensing DIDS involves coupling a fixed reference current loading to the drain node of the memory cell, to form a ratio-type sense amplifier. When control gate voltage is less than Vt for a cell, Ids for that cell will be less than a pre-selected reference current, which causes the sense amplifier output to be “1”. This sense amplifier reading indicates that the control gate voltage should be further increased, until a predetermined value exceeding the cell Vt is attained. When the control gate ramp voltage level exceeds the cell Vt, Ids will exceed the reference current, which pulls the sense amplifier output low, which allows the value of the cell data to be determined.
FIG. 2
is an exemplary graph of Ids distribution for a multi-level memory cell having sixteen levels of analog Vt values ranging from Vt
1
=1 V to Vt
16
=7.5 V, when applying drain voltage of 1 V and sweeping the control gate voltage VG. In Fazio-Wong systems, the sense amplifier output is almost digital in that large voltage swings occur. If there are sixteen Vt levels ranging from about 1 VDC to about 7.5 VDC, the &Dgr;Vt per storage level will be on the range of about 0.5 V. Referring to
FIG. 2
, assume that the reference current is selected as 40 &mgr;A. The horizontal row of black dots in
FIG. 2
represents the sixteen gate voltages required to read out the respective sixteen levels of Vt for the memory cell. Note that since cell current Ids is compared with a fixed reference current using a ramp-like gate voltage, a linear current difference between adjacent Vt levels can be maintained, along with a reasonable operating margin. Thus, Fazio-Wong type read out can offer advantages including improved read out resolution, and higher sense amplifier noise immunity margin. Typically a Fazio-Wong type system can implement perhaps thirty-two to one-hundred fifty-six levels of Vt per memory cell.
However, a significant drawback of the Fazio-Wong type sense scheme is the requirement for very accurate control gate voltage levels. For each ramp step, the control gate voltage must remain at a voltage level sufficiently long to attain a stable magnitude. Unfortunately this requirement decreases operating speed for the memory system, especially read access time. For a multi-level cell storing a large number of levels, i.e., 256 levels, read time can become excessive. As a result, the Fazio-Wong type approach shown in
FIGS. 1 and 2
is best suited to low-speed operations, such as the storage and playback for speech data.
Further, the long read process required in a Fazio-Wong type system increases the memory cell's exposure to stress. Typically read out operations for multi-level cells requires larger magnitude control gate voltage than for binary storage cells. As a result, as long as the control gate voltage is applied to a row, or word line in an array of memory cells, all cells on the row will experience stress from the large magnitude gate voltage, and can experience a shift in cell Vt value. Therefore, it is desired to reduce read time, to reduce exposure to stress and possible disturbance of cell Vt values.
In an attempt to overcome the above-mentioned slow speed problems, alternative sensing methods have been developed, for example as disclosed in U.S. Pat. No. 5,838,612 to Calligaro et al., and U.S. Pat. No. 5,220,531 to Blythe et al. Rather than use Fazio-Wong type low-speed, stepwise increased gate voltages, in systems according to Calligaro-Blythe, a fixed gate voltage is coupled directly applied to the control gate of the memory cell. The fixed-gate voltage causes memory cells having different values of Vt to conduct different magnitudes of cell Ids drain-source channel current. In Calligaro-Blythe type systems, the memory cell drain is connected to a reference current load, such as was described above with respect to Fazio-Wong. A differential output voltage is derived from the ratio between the cell Ids current and the reference current.
But the Calliagaro-Blythe approach has a significant drawback arising from the basic characteristic of MOS devices. In a MOS memory cell, the channel current distribution for each Vt level is not linear, but rather tends to saturate as gate voltage increases relative to magnitude of Vt for the cell.
FIG. 3
depicts cell current Ids for sixteen values of Vt (Vt
1
, Vt
2
, . . . Vt
15
, Vt
16
) for a fixed gate voltage, e.g., VG=8 VDC that is sufficiently high to turn-on all cells in the sixteen Vt range. Current distribution clearly is not linear. There is better

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