Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1998-11-13
2001-04-17
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S003000, C438S240000, C438S250000, C438S253000, C438S393000
Reexamination Certificate
active
06218258
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device with a high device packing density, and more particularly, a semiconductor device including a capacitor with an improved bottom electrode and a method for fabricating the same.
2. Description of Related Art
In general, a semiconductor memory device is provided with a driving transistor and a capacitor which stores information therein. A volatile memory device, such as a dynamic random access memory (DRAM), stores information as an amount of charge in the capacitor. The amount of charge stored in the memory device, such as a DRAM, can be increased as follows: fabricating a three dimensional capacitor to increase an effective area of the capacitor; reducing a thickness of a dielectric in the capacitor; and using a dielectric having a higher dielectric constant.
Because increasing the stored charge by increasing the surface area and reducing the thickness of the dielectric requires complicated fabrication process steps, these techniques for increasing the stored charge are not generally adopted. Instead, the stored charge is increased by using high dielectric constant dielectric films. As the high dielectric constant dielectric films, (Ba, Sr)TiO
3
and (Pb, La)(Zr,Ti)O
3
may be used. The high dielectric constant dielectric films BST[(Ba, Sr)TiO
3
] are mostly used in DRAMs, and the high dielectric constant dielectric films PZT(PbZrTiO
3
) are mostly used in flash random access memories (FRAMs). If a high dielectric constant dielectric film such as BST is deposited on a silicon substrate directly, the silicon oxidizes making a defective contact or the BST film degrades due to a reaction between BST and Si. Because of this, when high dielectric constant dielectric films such as BST are used as the dielectric of a capacitor, a metal film such as Pt, Ru and Ir, which is less reactive, is usually used as the bottom electrode of the capacitor. This is applicable to both DRAMs and FRAMs. Because a complicated three dimensional electrode is not required for increasing an effective area of the capacitor if a high dielectric constant dielectric film such as BST or PZT is used, a memory device having a device packing density greater than the giga class can be fabricated according to the simple structure shown in FIG.
1
.
As shown in
FIG. 1
, an interlayer insulation layer
2
is formed on a substrate
1
, and has a contact hole formed therein. A plug
3
fills the contact hole, and a barrier
4
is formed on the substrate
1
and the plug
3
. A bottom electrode
5
is formed on the barrier
4
, and a dielectric
6
covers the interlayer insulation layer
2
, the bottom electrode
5
and the barrier layer
4
. A top electrode (not shown) is then formed on the dielectric
6
.
When PZT or BST is used as the dielectric film
6
, one of Pt, Ru and Ir is used as the bottom electrode
5
. However, when Pt or Ru is used as the bottom electrode
5
, the electrical characteristics of the capacitor change.
FIGS. 2A and 2B
illustrates the use of Pt as the bottom electrode
5
. Pt has a great work function, which results in excellent electrical characteristics and reduced leakage current, but Pt is oxygen permeable. As a result, oxidation at the barrier
4
and plug
3
interface takes place to form an oxide layer
7
. Typically this oxidation consumes the barrier
4
. The oxygen diffuses mostly along the Pt grain boundaries during the formation of the dielectric
6
causing oxygen holes in the dielectric
6
, which degrades the electrical characteristics thereof. As shown in
FIG. 2B
, residue
8
from an etching process inhibits patterning.
FIG. 3
illustrates the use of Ru as the bottom electrode
5
. When the dielectric film
6
is deposited, oxygen is absorbed from the dielectric
6
by the bottom electrode
5
as the bottom electrode
5
oxidizes. This forms an oxygen depletion layer between the dielectric
6
and the bottom electrode
5
resulting in poor electrical performance. To prevent this, the bottom electrode
5
is usually oxidized prior to deposition of the dielectric
6
so that the oxide layer formed therein prevents further oxidation using the oxygen in the dielectric
6
. Typically, the Ru bottom electrode
5
is formed through etching with oxygen to form an oxide layer
9
, RuOx, at the surface of the Ru bottom electrode
5
as shown in FIG.
3
. Besides preventing the absorption of oxygen from the dielectric
6
, the oxide of Ru is conductive. But the oxide of Ru also forms a rugged deposition surface as shown in FIG.
2
B. Because of this rugged surface, the oxide layer
9
has poor electrical characteristics.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor device including a capacitor with an improved bottom electrode that overcomes the disadvantages and problems noted above with respect to the conventional art.
Another object of the present invention is to provide a semiconductor device including a capacitor with an improved bottom electrode and therefore improved electrical characteristics.
These and other objects are achieved by providing a semiconductor device having a capacitor with a bottom electrode, comprising: a substrate having an interlayer insulating layer formed thereon, the interlayer insulating layer having a contact hole formed therein, and a plug disposed in the contact hole; a first bottom electrode formed on a portion of the interlayer insulating layer and over the contact hole; a first oxygen diffusion barrier formed on the first bottom electrode; a second bottom electrode formed on the first oxygen diffusion barrier; and a third bottom electrode formed on sidewalls of the first bottom electrode, the first oxygen diffusion barrier and the second bottom electrode.
These and other objects are also achieved by providing a method of forming a semiconductor device having a capacitor with a bottom electrode, comprising: providing a substrate having an interlayer insulating layer formed thereon, the interlayer insulating layer having a contact hole formed therein, and a plug disposed in the hole; forming a first bottom electrode layer on the interlayer insulating layer over the hole; forming a first oxygen diffusion barrier layer on the first bottom electrode layer; forming a second bottom electrode layer on the first oxygen diffusion barrier layer; selectively removing portions of the second bottom electrode layer, the oxygen diffusion barrier layer and the first bottom electrode layer to form a bottom electrode pattern; and forming a third bottom electrode on sidewalls of the bottom electrode pattern.
REFERENCES:
patent: 5191510 (1993-03-01), Huffman
patent: 5555486 (1996-09-01), Kingon et al.
patent: 5566045 (1996-10-01), Summerfelt et al.
patent: 5985731 (1999-11-01), Weng et al.
patent: 5998250 (1999-12-01), Andricacos et al.
patent: 6017789 (2000-01-01), Sandhu et al.
patent: 6020233 (2000-02-01), Kim
patent: 6025223 (2000-02-01), Park
patent: 6027966 (2000-02-01), Saenger et al.
patent: 6046469 (1999-11-01), Yamazaki et al.
Chaudhari Chandra
Chen Jack
Hyundai Electronics Industries Co,. Ltd.
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