Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-06-21
2001-04-24
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185270
Reexamination Certificate
active
06222775
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor memories, and, more particularly, to FLASH-EPROMs (Erasable Progammable Read Only Memory) and EEPROMs (Electrically Erasable Progammable Read Only Memory) on the same chip.
BACKGROUND OF THE INVENTION
The development of nonvolatile memories based on the principle of trapping electrical charge in an isolated gate (floating) of a field effect transistor (cell) to modify its turn-on threshold, has had and continues to have an extremely important role in the achievement of ever increasing levels of compactness, speed and low consumption of integrated systems. The development of such memories is strictly tied to a parallel development of suitable fabrication technologies and to the physical mechanisms that can be practically exploited for injecting electrical charge into a floating gate through the isolating dielectric, which often forms the gate dielectric of the complete structure (transistor) of the cell.
Relevant mechanisms will now be described. The so called Fowler-Nordheim (FN) tunnelling mechanism is operative with relatively thin oxide layers and requires a strong electric field. The direct tunnelling mechanism (DT) is operative with relatively thin oxide layers and with a relatively low electric field, is important for the charge retention, and establishes the lower level of the gate oxide scaling in nonvolatile memories. The tunnelling mechanism (IN) is assisted by charge traps in the dielectric created from electrical stresses and which represent the principal mechanism of charge loss in flash cells and in EEPROM cells that have been subjected to numerous programming and erasing cycles. The hot channel carrier injection mechanism is operative throughout an ample range of dielectric thickness and electric field intensities. Of course the above mechanisms, with the exception of the last, may theoretically be exploited also for extracting charge from the floating gate, i.e. for erasing the cell, though the voltage levels must be compatible with the physical-electrical structure of the cell.
It is evident that the charge and discharge mechanism of the floating gate will dictate the structure of the memory cell and of the overhead circuitry, with particular regard to writing, reading and eventually also the erasing circuits of the memory. This imposes case-by-case precise requirements of voltage and current levels necessary for programming and eventually erasing data stored in the memory, besides those required for reading them.
The need of altering the content of the memory by single “words” (herein intended to indicate a unit of information composed of a certain number of bits, for example 8, 16, 32 etc.) without having to reprogram the entire memory as in the case of the so-called EPROM memories, and therefore the requirement of erasing certain selected cells while leaving unchanged the information content of other memory cells, has led to develop the so called EEPROM or E
2
PROM cells, acronyms for Electrically Erasable and Programmable Read Only Memory. Typically, the problem tied to the necessity of biasing the floating gate through its capacitive coupling with a control gate and the semiconducting substrate to charge the floating gate and eventually discharge the electrical charge stored therein, has been satisfied by realizing a capacitive coupling zone between the floating gate and the drain region of the substrate through a thin tunnelling oxide. Through such a tunnelling window the flow of electrons from the isolated gate to the drain region, both during an erasing and a programming phase, occurs by the so-called Fowler-Nordheim tunnelling mechanism, by applying a sufficiently high voltage of one sign or of the opposite sign.
As it is well known, bytewise erasability of EEPROM memories is achieved with a penalty in terms of compactness of the memory cell matrix, these cells being from three to four times larger than an EPROM cell, for the same fabrication technology, because they require the integration of a select transistor associated with each cell. The fabrication process of an EEPROM memory of known kind is notably much more complex than an EPROM process and the EEPROM memory requires relatively more complex overhead circuitry, as well as the integration of voltage multipliers.
The improvement of fabrication technologies has allowed a further reduction of the minimum thickness of the insulating oxide between an insulated gate and the monocrystalline silicon substrate while reliably ensuring a remarkable absence of defects, down to an average thickness of the oxide much smaller than 100 Å. The FLASH cell is programmable through a mechanism of injection of hot channel electrons into the isolated gate, by biasing the gate electrode (control gate) with a sufficiently high positive voltage (for example in the order of 12 V) and the drain with a voltage of about 6V, to produce in the channel region of the cell a strong electric field suitable to generate within the silicon a current of highly energetic (hot) electrons capable of overcoming the potential barrier at the interface with dielectric to be thereafter attracted towards the floating gate by the electric field.
Because of the extreme thinness of the gate dielectric, by applying a relatively high voltage (up to 12V depending on the fabrication technology) to the source while maintaining the other electrodes to ground potential, the electrons injected into the floating gate are able to cross the thin dielectric according to a Fowler-Nordheim tunnelling mechanism and “discharge” in the source region, during an erasing phase of the memory. The possibility of electrically erasing the memory device without removing it from the printed circuit card for exposing it to UV light has solved a most severe problem of EPROM memories. With the overcoming of this problem, all the intrinsic advantages of EPROM memories, such as the extreme compactness, speed and above all their low cost, have opened an extremely vast field of application.
On the other hand, given that normally the flash memories are block-erasable, there is the possibility during the erasing phase some cells, faster than others, that they be over-erased (depleted) and assume a negative threshold voltage. Since the memory cell has no select transistor, the presence of depleted cells causes reading errors. In fact the reading phase takes place by applying a positive voltage to the selected wordline, being all other wordlines grounded and verifying the current absorbed by the selected bitline. A depleted cell provides current even with its wordline grounded making all other cells of the same bit line be read as “1” even if they are programmed as “0”. For this reason, the erasing process of FLASH memories is intrinsically critical and is commonly carried out through a succession of erasing bias pulses followed by verification until completing the erasing of all the cells of the memory. This is done while avoiding inadvertently bringing some of the cells to a depletion state.
Upon completing the erasing phase, unlike the EEPROM cells, which being provided with a select transistor the read current of erased cells is not determined as much by the threshold voltage of the cells but by the current that can be provided by the select transistor, individual FLASH-EPROM cells assume a threshold voltage value that is non-uniform and constant, but is within a certain range of variation. In other words, there is a spread of the threshold values of the cells, the breath of which is tied also to parameters of the fabrication process. Such a spread of the threshold values of the cells must be taken into account by the overhead circuitry of the memory.
To obviate this drawback of FLASH-EPROM memories, a particular cell structure has been proposed, wherein each control gate line (wordline) of the memory overlies (it is capacitively coupled) only for a portion of its width on the relative floating gates of the cells of the row, while the other portion forms the gate of as many select transis
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Nguyen Tan T.
STMicroelectronics S.r.l.
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