Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-12-15
2001-05-15
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S195000, C365S189050
Reexamination Certificate
active
06233200
ABSTRACT:
BACKGROUND
This disclosure relates to a clock distribution network system.
A clock distribution network system distributes a precise clock generated by a phase-locked loop (PLL) to different units on a chip. The PLL cannot directly drive the clock load because it is often heavily loaded. For example, a typical clock load on a chip is about 300 pico-Farads.
The clock distribution network system includes sets of buffers, gates, and wire-lines that distribute the clock to the various units on a chip. The system provides optimal routing of the clock chosen to provide accurate timing. The system also provides efficient power management by enabling clock delivery to active units and disabling delivery to inactive units.
A PLL takes advantage of a negative feedback to constantly adjust the frequency and phase of an oscillator that may change or drift.
FIG. 1
is a simplified block diagram of a conventional PLL. The PLL includes a phase and frequency detector
100
, a loop filter (low pass)
101
, a voltage-controlled oscillator (VCO)
102
, and a feedback frequency divider
103
.
The phase and frequency detector
100
takes two signals as its inputs and outputs a voltage proportional to the difference between the frequencies of the two input signals.
The VCO
102
operates in reverse. It takes a voltage as its control input and outputs a signal having a frequency based on the value of the input voltage. Thus, during a PLL acquisition process, the VCO
102
is often sweeping through a wide range of frequencies. For example, the acquisition process may take less than 1 &mgr;S; during this period, the VCO output frequency sweeps through a range from a PLL steady state frequency of few hundred MHz to a very high frequency of several GHz.
SUMMARY
An apparatus comprising a distribution inhibit circuit is disclosed. The circuit selectively inhibits distribution of a clock signal responsive to a lock detect signal being de-asserted.
REFERENCES:
patent: 5886582 (1999-03-01), Stansell
Fayneh Eyal
Knoll Ernest
Fish & Richardson P.C.
Hoang Huan
Intel Corporation
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