Semiconductor device

Details Semiconductor device Semiconductor device

1998-11-25

2001-07-03

Picardat, Kevin M. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

C257S133000, C257S138000, C257S142000

Reexamination Certificate

active

06255672

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a switching element and, more particularly, to a semiconductor device having an improved mounting structure for thyristors, power transistors, and the like used in the field of power electronics.
Recently, in the field of power electronics control for industrial pumps, fans, and the like, efforts have been made to effectively use energy by using inverter devices. The major portion of such an inverter device is made of a semiconductor switching element for switching currents.
As semiconductor switching elements, thyristors, power transistors, and the like have been often used. Recently, a GTO (Gate Turn-off Thyristor), an IGBT (Insulated Gate Bipolar Transistor), an IEGT (Injection Enhanced Gate Transistor), and the like have been widely used.
Each of these semiconductor switching elements includes three electrodes, namely a positive (emitter) electrode, a negative (collector) electrode, and a control (gate) electrode, which are named differently depending on the types, and performs switching operation by controlling currents and voltages through the control electrode.
When these elements are mounted in a package, the positive and negative electrodes generate a considerable amount of heat because of the flow of large currents therein and switching operation. Careful consideration must therefore be given to current capacity and a heat dissipation structure. Since no large current flows in the control gate, no special heat dissipation measures are required for it.
In many cases, a plurality of semiconductor switching elements are simultaneously used depending on control targets.
FIG. 1
is a sectional side view of a conventional semiconductor device having a plurality (one pair in
FIG. 1
) of IGBTs (or IEGTs) as semiconductor switching elements mounted side by side on a board.
Two IGBTs
1
a
and
1
b
respectively have emitter electrodes
2
a
and
2
b
formed on their surfaces. The emitter electrodes
2
a
and
2
b
are respectively connected to wirings
10
a
and
10
b
by soldering.
Gate electrodes
6
a
and
6
b
are formed on the end faces of the upper surfaces of the IGBTs
1
a
and
1
b
. The gate electrodes
6
a
and
6
b
are respectively connected to wirings
10
c
and
10
d
by soldering.
Collector electrodes
9
a
and
9
b
are formed on the lower surfaces of the IGBTs
1
a
and
1
b
. The collector electrodes
9
a
and
9
b
are respectively connected to surface copper patterns
14
a
and
14
b
on a DBC (copper-clad ceramic) board
3
by soldering.
The electrodes
2
a
,
2
b
,
6
a
, and
6
b
on the upper surfaces of the IGBTs
1
a
and
1
b
and the electrodes
9
a
and
9
b
on the lower surfaces are metallized to allow soldering.
Note that a metallization method is not limited to a specific one, and a method of forming a metal layer on the surface of an aluminum electrode using titanium, platinum, gold, or palladium, a method of coating an aluminum electrode with nickel or the like, is properly used. A heat sink
12
is soldered to the lower surface of the board.
In this structure, the emitter electrode
2
a
on the IGBT
1
a
is electrically connected to the collector electrode
9
b
on the IGBT
1
b
through the wiring
10
a
and the surface copper pattern
14
b.
FIG. 2
is a sectional side view of another conventional semiconductor device having a plurality (one pair in
FIG. 2
) of IGBTs mounted on a board.
Two IGBTs
1
a
and
1
b
respectively have emitter electrodes
2
a
and
2
b
formed on their lower surfaces. The emitter electrodes
2
a
and
2
b
are respectively connected to surface copper patterns
14
a
and
14
b
on a DBC (copper-clad ceramic) board
3
by soldering.
Gate electrodes
6
a
and
6
b
are formed on the end faces of the upper surfaces of the IGBT
3
1
a
and
1
b
. The gate electrodes
6
a
and
6
b
are respectively connected to surface copper patterns
7
a
and
7
b
on the DBC board
3
by soldering.
Collector electrodes
9
a
and
9
b
are also formed on the lower surfaces of the IGBTs
1
a
and
1
b
. The collector electrodes
9
a
and
9
b
are respectively connected to wirings
10
d
and
10
c
by soldering.
The electrodes
2
a
,
2
b
,
6
a
,
6
b
,
9
a
, and
9
b
on the upper and lower surfaces of the IGBTs
1
a
and
1
b
are metallized to allow soldering as in the case shown in FIG.
1
. Similarly, a heat sink
12
is also soldered to the lower surface of the board
3
.
In this structure, the emitter electrode
2
b
on the IGBT
1
b
is electrically connected to the collector electrode
9
a
on the IGBT
1
a
through the wiring
10
d
and the surface copper pattern
14
b.
In each of the conventional mounting structures shown in
FIGS. 1 and 2
, each connection member has a connect portion perpendicular to the board
3
. Therefore, a large inductance component is produced by each connect portion that is perpendicular to the board
3
.
In addition, since connection members such as the wirings
10
a
and
10
d
must be arranged between two chips, the size of the package becomes large.
If wirings are routed in a complicated manner to reduce a size of the package, connection members need not necessarily be arranged between two chips. In consideration of wiring resistances and inductances as electric circuit characteristics, however, it is inadvisable to route the interconnections in a complicated manner.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation, and has as its object to provide a semiconductor device which can omit wirings as connection members, which are perpendicular to a board by mounting a pair of semiconductor switching elements such that the upper side of one element faces in a direction opposite to that of the other element, thereby preventing increases in inductance and wiring resistance.
In order to achieve the above object, according to the present invention, there is provided a semiconductor device comprising:
a pair of semiconductor switching elements, each of the semiconductor switching elements having a positive electrode and control electrode formed on one surface and a negative electrode formed on the other surface; and
a board to which the positive and control electrodes of one of the semiconductor switching elements are joined and the negative electrode of the other semiconductor switching element facing in a direction opposite to that of one semiconductor switching element is joined.
With the above arrangement, according to the semiconductor device of the present invention, since the plurality of semiconductor switching elements are mounted on the land of the board in opposite directions, the components of the connect members which are perpendicular to the board can be omitted, thereby preventing increases in inductance and wiring resistance.
In addition, since any connect members or wirings need not be arranged between the two semiconductor switching elements, the distance between the semiconductor switching elements can be reduced, thereby reducing the package size.
The use of the conductors as connect members which are formed by weaving thin conducting wires allows a reduction in the rigidity of each electrode and hence can reduce thermal stress in each electrode, thereby preventing the element joint portions and the like from being damaged by fatigue while maintaining the advantages of a flat wiring structure with a low wiring inductance.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


REFERENCES:
patent: 5828100 (1998-10-01), Tamba et al.
patent: 33 22 593 (1985-01-01), None
patent: 9-64258 (1997-03-01), None
Patent Abstracts of Japan, vol. 018, No. 686(C-1292), Dec. 26, 1994, JP 06 272147, Sep. 27, 1994.

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