Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-08-18
2001-08-07
Mills, Gregory (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S424000, C438S427000, C438S428000, C438S692000, C438S734000, C438S704000, C438S753000, C438S719000, C438S749000
Reexamination Certificate
active
06271147
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to trench isolation methods for integrated devices. More particularly, it relates to methods of forming trench isolation regions using spin-on material.
2. Description of the Related Arts
Device isolation techniques play an important role in the design and performance of highly integrated semiconductor circuits by electrically isolating regions and devices therein from adjacent devices and regions. Moreover, as the degree of integration in semiconductor circuits increases, there is a concomitant need to develop techniques for forming isolation regions which are free of defects and can be scaled to provide isolation regions having smaller dimensions, but without sacrificing the isolation capability of the regions.
One widely used and relatively simple technique for providing device isolation is typically referred to as local oxidation of silicon (LOCOS). Unfortunately, this technique has a number of disadvantages because it typically includes the formation of bird's beak oxide extensions, induces lattice stress which can lead to the formation of crystal defects in semiconductor substrates, and causes redistribution of channel-stop dopants. As will be understood by those skilled in the art, these disadvantages typically cause a reduction in the lateral area available for active devices, and degrade the reliability and performance of devices formed in adjacent active regions.
Another method which may be considered an improvement over the LOCOS method is typically referred to as the shallow trench isolation (STI) method. In the STI method, a device isolation region is established by selectively etching a semiconductor substrate to form trenches therein and then filling the trenches with an electrically insulating region (e.g., oxide). A chemical etching and/or chemical-mechanical polishing (CMP) step can then be performed to planarize the electrically insulating region to be level with the surface of the substrate. Because the STI method typically does not include a lengthy thermal oxidation step as typically required by the LOCOS method, many of the disadvantages of the LOCOS method can be eliminated to some degree. However, as will be understood by those skilled in the art, the STI method may be prone to a “dishing” phenomenon which can degrade the isolation characteristics of trench isolation regions.
Hereinafter, a conventional trench isolation method for a semiconductor device will be described with reference to
FIGS. 1 through 6
. First, referring to
FIG. 1
, a pad oxide layer
12
and a nitride layer
14
are deposited on a semiconductor substrate
10
in sequence. The pad oxide layer
12
functions as a protection layer for an active region during the formation of a trench. Then, a photoresist pattern
16
, for defining a region in which the trench is to be formed, is formed on the nitride layer
14
. Then, as shown in
FIG. 2
, the nitride layer
14
and the pad oxide layer
12
are etched in sequence using the photoresist pattern
16
as an etching mask to form a nitride layer pattern
14
A and a pad oxide layer pattern
12
A. Then, the semiconductor substrate
10
is dry-etched to form a trench
17
with a predetermined depth. Next, as shown in
FIG. 3
, after removing the photoresist pattern
16
, an oxide layer
18
is formed on the nitride layer pattern
14
A with a predetermined thickness while completely filling the trench
17
, using a chemical vapor deposition (CVD) method.
Then, as shown in
FIG. 4
, the oxide layer
18
is planarized by a chemical mechanical polishing (CMP) process, using the surface of the nitride layer pattern
14
A as a planarization stop, to form a field oxide layer pattern
18
A. Thereafter, as shown in
FIG. 5
, the nitride layer pattern
14
A and the pad oxide layer pattern
12
A are removed to define the trench isolation region
18
A. Then, a sacrificial oxidation process and a cleaning process are performed to complete a trench isolation region
18
B as shown in FIG.
6
.
However, according to the conventional trench isolation method, the edge portion of the oxide layer filling the trench is also etched by the sacrificial oxidation process or the cleaning process, showing a profile such as portion “A” shown in FIG.
6
. That is, the device isolation region is slanted at the upper boundary between the active region and the device isolation region, so that a gate oxide layer becomes thinner at the boundary and an electric field is concentrated thereon. Also, stress may be applied to an upper insulation region to be formed in a following step. This stress can promote the generation of leakage currents and otherwise deteriorate the characteristics of the devices formed in adjacent active regions.
Thus, it would be highly desirable to be able to provide trench isolation regions which are less susceptible to edge defects.
U.S. Pat. No. 5,966,614 discloses simplified trench isolation methods for integrated circuit devices. However, the methods disclosed in U.S. Pat. No. 5,966,614 will degrade performance of MOS transistors due to sharp edge on trench corner after dipping of sacrificial oxide (see first and second embodiment of U.S. Pat. No. 5,966,614).
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide improved methods of forming trench isolation regions in semiconductor substrates which are less susceptible to edge defects.
It is another object of the invention to provide simplified methods of forming trench isolation regions by eliminating the formation, etching and removal of silicon nitride.
It is yet another object of the invention to provide simplified trench isolation methods, by which improved performance of integrated circuits can be obtained.
To attain the above and other objects, the present invention provides methods of forming trench isolation regions by using spin-on material as a trench insulating layer. In one embodiment, a photoresist pattern having an opening therein is directly formed on a bare semiconductor substrate. The bare semiconductor substrate is etched through the opening in the photoresist pattern to form a trench in the substrate. The photoresist pattern is isotropically etched to enlarge the size of the opening. A spin-on material layer is coated overlying the substrate surface to completely fill the trench and the enlarged opening, and then etched back until the photoresist pattern is exposed. After removing the photoresist pattern from the bare semiconductor substrate, the spin-on material layer is cured by a thermal treatment to form a trench isolation region.
After formation of the trench isolation region, a sacrificial oxide layer may be formed on substrate surface and ions may be implanted through the oxide layer. The ions may be used to form wells and channel stops and to control the threshold voltage of devices that are subsequently formed.
According to a feature of the present invention, trench isolation regions can be formed having reduced susceptibility to edge defects because the periphery of the trench at the face of the substrate is covered by the insulating material.
According to another feature of the present invention, conventional trench isolation methods are simplified by eliminating silicon nitride layer.
According to yet another feature of the present invention, the trench insulating layer is deposited in the presence of the photoresist pattern, and thereafter cured in the absence of the photoresist pattern.
According to a further feature of the present invention, the manufacturing cost can be reduced because the insulating materials formed by a spin-coating process cost much less than those by chemical vapor deposition (CVD) techniques.
REFERENCES:
patent: 5899716 (1999-05-01), Tseng
patent: 5963819 (1999-10-01), Lan
patent: 5966614 (1999-10-01), Park et al.
patent: 6074931 (2000-06-01), Chang et al.
patent: 6080637 (2000-06-01), Huang et al.
patent: 6093621 (2000-07-01), Tseng
patent: 08-288256 (1996-11-01), None
Darby & Darby
Goudreau George
Mills Gregory
Vanguard International Semiconductor Corporation
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