Method of forming buried bit line memory circuitry and...

Details Method of forming buried bit line memory circuitry and... Method of forming buried bit line memory circuitry and...

1999-12-06

2001-06-12

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S256000, C438S643000, C438S648000, C438S649000

Reexamination Certificate

active

06245631

ABSTRACT:

TECHNICAL FIELD
This invention relates to methods of forming buried bit line memory circuitry and to semiconductor processing methods of forming conductive lines.
BACKGROUND OF THE INVENTION
Semiconductor circuitry fabrication is ever attempting to make denser and smaller circuit components. One type of circuitry where this is occurring is in the design and fabrication of memory circuitry, for example in buried bit line memory circuitry. One type of memory circuitry employing buried bit line architecture is dynamic random access memory (DRAM). Such circuitry typically includes a series of bit lines and word lines wherein at least a majority portion of the capacitors are formed elevationally above or outwardly of the bit lines.
A parasitic capacitance between buried digit lines becomes increasingly problematic as circuitry density becomes greater and circuitry components become smaller. Accordingly, alternate designs and materials are being considered for fabrication of the digit lines in highly dense circuitry fabrication, for example at and below 0.18 micron digit line width.
The invention was motivated from a desire to improve fabrication methods and constructions associated with buried bit line circuitry, and particularly buried bit line DRAM circuitry. However, the artisan will appreciate applicability of the invention to other circuitry fabrication methods and structures, with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the doctrine of equivalents.
SUMMARY
The invention includes methods of forming buried bit line memory circuitry and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing method of forming a conductive line includes forming a silicon comprising region over a substrate. A TiN
x
comprising layer is deposited over the silicon comprising region, where “x” is greater than 0 and less than 1. The TiN
x
comprising layer is annealed in a nitrogen and hydrogen plasma atmosphere effective to transform at least an outermost portion of the TiN
x
layer over the silicon comprising region to TiN. After the annealing, an elemental tungsten comprising layer if formed on the TiN and at least the elemental tungsten comprising layer, the TiN, and any remaining TiN
x
layer is patterned into conductive line. In one implementation, a method such as the above is utilized in the fabrication of buried bit line memory circuitry.


REFERENCES:
patent: 5187120 (1993-02-01), Wang
patent: 5329153 (1994-07-01), Dixit
patent: 5525543 (1996-06-01), CHen
patent: 5760475 (1998-06-01), Cronin et al.
patent: 5913145 (1999-06-01), Lu et al.
patent: 5985759 (1999-11-01), Kim et al.
patent: 6093638 (2000-07-01), Cho et al.
patent: 6159851 (2000-12-01), Chen et al.
patent: B1 6174798 (2001-01-01), Hsia et al.
U.S. application No. 09/454,536, Hu et al.
U.S. application No. 09/026,104, Hu et al, filed Feb. 1998.
U.S. application No. 09/259,216, Hu et al., filed Mar. 1999.
U.S. application No. 09/260,237, Hu et al., filed Mar. 1999.

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