SOI CMOS sense amplifier with enhanced matching...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude

Reexamination Certificate

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Details

C327S055000

Reexamination Certificate

active

06222394

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) sense amplifier with improved matching characteristics and sense point tolerance.
DESCRIPTION OF THE RELATED ART
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. By utilizing SOI technology, designers can increase the speed of digital logic integrated circuits or can reduce their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.
As shown in
FIG. 1
, SOI semiconductors include a thin layer of silicon placed on top of an insulator, such as silicon dioxide (SiO
2
) or glass, and a MOS transistor built on top of this structure. The main advantage of constructing the MOS transistor on top of an insulator layer is to reduce the internal capacitance of the transistor. This is accomplished by placing the insulator oxide layer between the silicon substrate and the impurities required for the device to operate as a transistor. Reducing the internal capacitance of the transistor increases its operating speed. With SOI technology, faster MOS transistors can be manufactured resulting in faster electronic devices.
A problem called bipolar discharge exists with SOI FETs. An inherent drawback of placing a MOS transistor on top of a SOI layer is that the MOS transistor is actually placed in parallel with a parasitic bipolar junction transistor, as illustrated in FIG.
2
. The parasitic bipolar transistor can cause the unwanted effect called bipolar discharge, which alters the speed and lowers noise margin in a dynamic CMOS circuit.
Normally, parasitic bipolar action does not manifest itself in conventional bulk CMOS transistors because the base of the bipolar transistor is always kept at ground potential, keeping the bipolar transistor turned off. In the SOI FET, the body (B) of the MOS FET device, or base of the bipolar transistor, is floating and can be charged high by junction leakages induced when, both drain (D) and source (S) terminals of the MOS FET are at a high potential. Subsequently, if the source (S) is pulled to a low potential, the trapped charge in the body (B) is available as base current for the parasitic bipolar transistor. The parasitic base current activates the bipolar transistor and generates a collector current at the drain terminal of the MOS FET. This collector current flow in the bipolar junction transistor or bipolar discharge is undesirable since it causes an unintended loss of charge on the drain node of a dynamic circuit. Such bipolar discharge reduces the noise margin of the dynamic circuit and can result in the functional failure.
Dynamic and dual rail silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits are prone to performance variation and mismatch in transfer characteristics due to body potential and threshold voltage differentials. This is a direct result of circuit operating history and dissimilar time constants to charge and discharge field effect transistor (FET) bodies as compared with the actual access times or cycle times. Repetitive read operations performed on a sense amplifier over time can result in significant body potential bias, and consequently mismatches in FET threshold voltage and amplifier transfer characteristics. This degrades the circuit noise margin, reduces the differential gain and switching sensitivity of the amplifier, lowers performance, and can potentially cause logic faults.
A need exists for a silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) sense amplifier with improved matching characteristics and sense point tolerance.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) sense amplifier with improved matching characteristics and sense point tolerance. Other important objects of the present invention are to provide such a silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) sense amplifier with improved matching characteristics and sense point tolerance substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) sense amplifier is provided with improved matching characteristics and sense point tolerance while simultaneously achieving high performance. The sense amplifier includes a silicon-on-insulator (SOI) field effect transistor. A flooding field effect transistor is coupled to a body of the silicon-on-insulator (SOI) field effect transistor. The flooding field effect transistor is activated before the sense amplifier is set.
In accordance with features of the invention, the flooding field effect transistor has an opposite polarity of the silicon-on-insulator (SOI) field effect transistor. The flooding field effect transistor provides a charging path to a voltage supply rail. A pair of flooding field effect transistors serve as charging to voltage supply rail elements for silicon-on-insulator (SOI) field effect transistors on each side of complementary bitline structures of the sense amplifier. The flooding field effect transistor is substantially smaller than the silicon-on-insulator (SOI) field effect transistor.


REFERENCES:
patent: 5581106 (1996-12-01), Hayashi et al.
patent: 6037808 (2000-03-01), Houston et al.
patent: 6061267 (2000-05-01), Houston

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