Reducing metal voids during BEOL metallization

Details Reducing metal voids during BEOL metallization Reducing metal voids during BEOL metallization

1998-09-24

2001-01-23

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

C438S016000, C438S622000, C438S624000

Reexamination Certificate

active

06177286

ABSTRACT:

TECHNICAL FIELD
The present invention relates, in general, to the process of making back end of the line (BEOL) semiconductor device interconnections and, more specifically, to a process for reducing the metal voids in metal lines for BEOL semiconductor devices.
BACKGROUND OF THE INVENTION
Methods for fabricating metal lines for back end of the line (BEOL) applications in semiconductor devices are well known in the art. For example,
FIG. 1
illustrates a typical fabrication of two metal lines in BEOL semiconductor device
10
and involves patterning of a metal layer using is lithography and metal reactive ion etch (RIE) techniques. A bottom barrier blanket layer, such as a Ti or TiN layer, is deposited on top of interlevel dielectric
11
. This bottom barrier blanket layer is followed by deposition of a high conductivity metal, usually A
1
with 0.5% Cu. The high-conductivity layer is then covered by depositing a top barrier blanket layer, such as a Ti or TiN layer.
A photoresist layer is patterned into a mask (not shown) over portions of the layers in a known fashion. After photoresist exposure, the masking material (photoresist in this case) is removed in areas where the metal is to be removed by the RIE process. One such structure produced after the RIE process is shown in FIG.
1
. As shown, the structure contains (1) metal line
12
a
sandwiched between top barrier
13
a
and bottom barrier
14
a,
and (2) metal line
12
b
sandwiched between top barrier
13
b
and bottom barrier
14
b.
Following patterning of the final metal layer, a passivation layer (not shown) is deposited over the entire top surface of the wafer. This is an electrically insulating and protective layer that prevents mechanical and chemical damage during assembly and packaging of the wafer. Thus, metal lines
12
a
and
12
b
are usually encapsulated by a dielectric deposition of oxides. These oxides may be deposited by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or high density plasma (HDP) deposition.
It has been observed that voids may occur in the is metal lines due to some process imperfection. The voids may appear on one side of the metal line or on both sides of the metal line. It has been believed that these voids occur because of “undercut” conditions during the RIE process. Because the voids are imperfections in the metal lines, they contribute to decreasing the reliability of the semiconductor.
It is also known that dielectrics such as HDP, CVD, and PECVD oxides, used commonly in the semiconductor industry for BEOL passivation, exert compressive stress (expressed as a negative force pushing down) on the metal lines. The compressive stress may also be a factor in producing voids in the metal lines. The stress-induced voids also contribute to the reduced reliability of the semiconductor device.
The deficiencies of the conventional processes used to make metal lines in BEOL semiconductor devices show that a need still exists for a process which can reduce or eliminate the metal voids created in these metal lines after the metal layer has been deposited on the substrate.
SUMMARY OF THE INVENTION
To meet this and other needs, and in view of its purposes, the present invention provides a process for making metal lines in BEOL semiconductor devices. The process reduces metal voids in the metal lines and, in one embodiment, includes the following steps:
(a) metal lines, including a top barrier blanket, are formed over an interlevel dielectric,
(b) an insulating layer having tensile stress properties is formed over the metal lines,
(c) a first compressive oxide layer is formed over the insulating layer, wherein the insulating layer provides a tensile stress on the metal lines and the compressive oxide layer provides a compressive stress on the metal lines resulting in reduction of metal voids,
(d) the compressive oxide layer is etched with one type of gas until the insulating layer is reached,
(e) the insulating layer is etched with a second gas until the top barrier blanket is reached,
(f) the second gas is monitored for an intensity level at a wavelength optical emission, and
(g) the etching is stopped when the intensity level is reached.
It is understood that the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.


REFERENCES:
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patent: 5652465 (1997-07-01), Hosada et al.
patent: 5716872 (1998-02-01), Isobe
patent: 5759906 (1998-06-01), Lou
patent: 5905298 (1999-05-01), Watatani
patent: 5955380 (1999-09-01), Lee
Wolf et al., Silicion Processing for the VLSI Era, vol. 1: Process Technology, pp. 567, 567, 1986, month unknown.

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