Power transistor with silicided gate and contacts

Details Power transistor with silicided gate and contacts Power transistor with silicided gate and contacts

1998-10-07

2001-09-04

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S723000, C438S725000, C438S755000, C438S756000, C438S785000

Reexamination Certificate

active

06284669

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of electronic devices and more particularly to a MOS power transistor having a silicided gate and contacts and a method of forming the same.
BACKGROUND OF THE INVENTION
Field effect transistors that are used in power applications or RF applications must switch significant amounts of current at very high frequencies. The downscaling of these field effect transistors helps reduce the total source to drain resistance and the junction capacitances; both can enhance the power handling capability of the device at high frequencies. As the transistor scales to smaller channel lengths, the gate linewidth gets narrower and the sheet resistance contribution to the RC delay increases, drastically impacting the performance in an RF application. While power transistors do not necessarily have to switch at high speeds, this RC delay increase impacts how uniformly the transistor switches. If a power transistor does not uniformly switch, localized regions of the transistor may be required to conduct more current than can reliably be handled, resulting in destruction of the power transistor. Because of these requirements, various solutions for the processing of low resistivity gate material in conjunction with low resistivity contacts to the source and drain of the transistor have been explored.
One approach for obtaining low resistivity gate material is to use refractory metals such as molybdenum. While providing an extremely low resistivity, molybdenum does require special processing and care such that the deposited film does not lead to unwanted traps in the gate oxide, is completely passivated from oxidizing ambients, and there is a means to reliably etch the material for pattern generation. Also, the molybdenum gate does not address the low contact resistance required in the source and drain regions.
Another approach uses tungsten silicide to form the low resistivity gate of the field effect transistor. Tungsten silicide is able to withstand high process temperatures and provides a resultant resistivity of approximately 70E-6 ohm-cm. This silicide is formed through a cosputtering process of the mixture of metal and silicon. The stability of tungsten silicide during high temperature processing and its means of deposition make it suitable for a polycide process, but it also does not address the source and drain contact regions.
As opposed to the polycide processing, many low-power, low-voltage technologies utilize techniques that silicide the polysilicon gates as well as the active source and drain regions of the transistor. This provides both improved gate resistivity and reduced source/drain resistance required for fast switching. A shortcoming of this approach is that it precludes the manufacturing of high-voltage components as the silicide in both the source and drain regions is adjacent to the poly gate spaced by the sidewall oxide. This results in low voltage transistors through the impact of BVdss. Typical materials used in these techniques are titanium and platinum. Titanium-silicide has a resistivity of approximately 13E-06 to 16E-06 ohm-cm, while platinum-silicide has a resistivity of approximately 28E-06 to 35E-06 ohm-cm. Neither of these materials can withstand the high temperature processing as tungsten silicide can, so this temperature limitation forces the processing to be near the end of the manufacturing process where temperature budgets are much less.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a power field effect device which uses platinum silicide to reduce the sheet resistance of the gate, and the contact resistance of the source and drain of the device, but which must keep the platinum silicide regions at a safe distance from one another to prevent low voltage breakdown of the device.
In accordance with the teachings of the present invention, a power transistor is provided that substantially eliminates or reduces disadvantages associated with prior systems and processing methods. According to one embodiment of the present invention, a power transistor is provided that comprises a drain region containing a platinum silicide layer formed in contact with the drain region. The transistor also comprises a gate body having a platinum silicide layer formed in contact with the gate body. The drain region and the platinum silicide drain contact layer are spaced apart from the gate body and the platinum silicide gate contact layer.


REFERENCES:
patent: 4686000 (1987-08-01), Heath
patent: 4769686 (1988-09-01), Horiuchi et al.
patent: 4908688 (1990-03-01), Lund et al.
patent: 5621232 (1997-04-01), Ohno
patent: 5728619 (1998-03-01), Tsai et al.

Affiliated with

Also associated with

Rating

Power transistor with silicided gate and contacts does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power transistor with silicided gate and contacts, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power transistor with silicided gate and contacts will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2467286