Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
1999-01-12
2001-03-06
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
Reexamination Certificate
active
06197620
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to integrated circuit memory design, and in particular to dynamic random access memory design.
BACKGROUND OF THE INVENTION
Dynamic Random Access Memory (DRAM) devices are the most widely used type of memory device. The amount of singlebit addressable memory locations within each DRAM is increasing as the need for greater memory part densities increases. This demand for greater memory densities has created a global market and has resulted in memory part standards in which many memory parts are regarded as fungible items. Thus, many memory parts operate according to well known and universally adopted specifications such that one manufacturers memory part is plug-compatible with another manufacturer's memory part.
There is a need in the art to produce memory parts which can fit within the packaging requirements of previous generations of memory parts. This need for “plug-compatible upgrades” requires that memory density upgrades are easy to effect in existing computer systems and other systems which use memory, such as video systems. This requires that greater density memory parts be placed within the same size packages as previous generations of memory parts with the same signal and power pinout assignments.
There is a further need in the art to more efficiently manufacture CMOS dynamic random access semiconductor memory parts which utilize space-saving techniques to fit the most memory cells within a fixed die size using a single deposition layer of highly conductive interconnect. There is a need in the art to manufacture such memory parts in a shorter production time using fewer process steps to produce more competitively priced memory parts.
SUMMARY OF THE INVENTION
The present invention solves the above-mentioned needs in the art and other needs which will be understood by those skilled in the art upon reading and understanding the present specification. The present invention includes a memory having at least 16 megabits (2
24
bits) which is uniquely formed in which highly conductive interconnects (such as metal) are deposited in a single deposition step. The invention is described in reference to exemplary embodiments of 16 and 32 Megabit Dynamic Random Access Memory in which only a single deposition layer of highly conductive interconnects are deposited in a single deposition step. The resulting semiconductor die or chip fits within existing industry-standard packages with little or no speed loss over previous double metal deposition layered DRAM physical architectures. This is accomplished using a die orientation that allows for a fast single metal speed path. The use of a single deposition layer metal design results in lower production costs, and shorter production time for a wide variety of memory parts, including but not limited to, DRAM, SDRAM, SRAM, VRAM, SAM, and the like. In addition, the architecture can be easily replicated to provide larger size memory devices.
According to one aspect of the present invention, a method of reducing parasitic resistance in an n-sense amplifier is described in which a ground bus is connected through row decoder logic to the n-sense amplifier.
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Bowers Charles
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Thompson Craig
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