Oscillator circuit controlled by programmable logic

Details Oscillator circuit controlled by programmable logic Oscillator circuit controlled by programmable logic

1999-05-26

2001-01-23

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S00100A, C331S016000, C331SDIG002, C327S156000, C327S159000

Reexamination Certificate

active

06177843

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a oscillators generally and, more particularly, to a method, architecture, and circuit for controlling and/or operating an oscillator.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, an example of a conventional phase locked loop circuit
10
is shown. The circuit
10
generally comprises phase frequency detector
12
, a charge pump/filter
14
, a clamp
15
, an oscillator
16
and a divider
18
. The circuit
10
is used to multiply a reference signal REFCLK having a fixed frequency, received at an input
24
, by some multiple set by the divider
18
. The phase frequency detector
12
is coupled to the oscillator
16
through the charge pump/filter
14
. The divider circuit
18
has an input
28
that receives a feedback of the signal VCO_OUT presented at an output
29
of the oscillator
16
. The divider
18
presents a signal to the input
30
of the phase frequency detector
12
. The phase frequency detector
12
is capable of indicating both phase error and frequency error. Errors coupled through the charge pump/filter
14
cause the VCO
16
to change the frequency of the signal VCO_OUT to minimize the error. VCO frequency errors may be managed by the circuit
10
. The nominal frequency of operation of the signal VCO_OUT will be the frequency of the reference signal REFCLK multiplied by the divider ratio. A typical phase frequency detector
12
, as used in the circuit
10
, cannot tolerate irregular input data streams that may be found in a serial data input. As a result, the circuit
10
may not be an adequate solution for the VCO frequency error problem. The circuit uses an analog clamp
15
, which is difficult to optimize across a wide range of frequencies at the output. Also, the voltages presented by the clamp
15
are difficult to control.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising an oscillator circuit and a logic circuit. The oscillator circuit may be configured to present an output signal having a frequency in response to (i) a reference signal, (ii) a control signal and (iii) the output signal. The logic circuit may be configured to present the control signal in response to (i) the output signal and (ii) the reference signal. In one example, the logic circuit may disable the oscillator when the output signal oscillates outside a predetermined range.
The objects, features and advantages of the present invention include providing a circuit, architecture and/or method for controlling and/or operating an oscillator that may (i) prevent a runaway condition, (ii) use logic to sample the frequency difference between two clocks to compare with programmed thresholds to generate a control signal, (iii) provide a circuit with an adjustable granularity and/or (iv) may provide an auto-clearing mechanism.


REFERENCES:
patent: 4646031 (1987-02-01), Fast et al.
patent: 4943788 (1990-07-01), Laws et al.
patent: 4996444 (1991-02-01), Thomas et al.
patent: 5138281 (1992-08-01), Boudewijns
patent: 5254955 (1993-10-01), Saeki et al.
patent: 5406592 (1995-04-01), Baumert
patent: 5629651 (1997-05-01), Mizuno
patent: 5694087 (1997-12-01), Ferraiolo et al.
patent: 5699020 (1997-12-01), Jefferson

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