Semiconductor device and method of fabricating the same

Details Semiconductor device and method of fabricating the same Semiconductor device and method of fabricating the same

1998-07-13

2001-07-31

Lee, Thomas (Department: 2182)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C716S030000

Reexamination Certificate

active

06269280

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device comprising a logic integrated circuit (hereinafter referred to as a logic) and a dynamic random access memory (hereinafter referred to as a DRAM) which are mounted on a single chip. Throughout this specification, it is assumed that the concept of the logic includes a central processing unit (hereinafter referred to as a CPU).
2. Description of the Background Art
FIG. 19
is a conceptual diagram showing an exemplary structure of a semiconductor device comprising a DRAM and a logic which are formed on a plurality of chips
1
and
2
. Signal lines
3
connect the chips
1
and
2
provided with the DRAM and the logic respectively with each other. Since a fabrication method suitable for improving the performance of the DRAM is different from that suitable for improving the performance of the logic, it is common to form the DRAM and the logic on the different chips
1
and
2
, which in turn are connected with each other by the signal lines
3
as shown in FIG.
19
.
In case of exchanging data processed by the chips
1
and
2
provided with the DRAM and the logic through the signal lines
3
, however, the processing speed of the semiconductor device is limited. In order to solve this problem, a DRAM
5
and a logic
6
can be provided on a single chip
4
as shown in
FIG. 20
, for improving the speed of the semiconductor device. A semiconductor device such as that shown in
FIG. 20
is hereinafter referred to as an embedded RAM, which is abbreviated as eRAM. The DRAM
5
provided in the eRAM is different in tendency of production, countermeasures for improving productivity and tendency of specifications from the DRAM mounted on the single chip
1
. Table
1
shows such differences.
TABLE 1
In Case of Implementing
In Case of Embedding
DRAM with Single Chip
DRAM in eRAM
Tendency of
Small Variety/
Large Variety/
Production
Mass Production
Small-Lot Production
Countermeasures
Improvement of
Reduction of Term of
for Improving
Yield/Miniaturization
Works in Addition to
Productivity
Improvement of Yield
Tendency of
Standardization
Partial Discrimination
Specification
However, the design of an eRAM is often changed in the process of fabricating the product, due to partial discrimination of specifications for each customer. Such eRAMs are generally produced in a small lot in response to the order of the customer. Further, eRAMs are developed in a large variety as compared with DRAMs which are formed on single chips. The DRAMs formed on single chips are mass-produced, and hence improvement of productivity is achieved by miniaturization. In order to improve the productivity of the eRAMs which are produced in response to the order of the customer, on the other hand, it is an important subject to reduce the time required to design and layout the circuit, also referred to as the term of works. Such reduction of the term of works is implemented by computerizing noncomputerized design or reducing the time for computer aided design.
FIG. 21
is a flow chart showing fabrication steps for an eRAM from decision of specifications to mass production. Referring to
FIG. 21
, steps ST
1
, ST
2
, ST
3
, ST
4
, ST
5
and ST
6
are adapted to decide the specifications, to design architecture in response to the decided specifications, to design the logic and the circuit on the basis of the designed architecture, to design the layout on the basis of circuit connection information created at the step ST
3
, to prepare a mask on the basis of a layout diagram created at the step ST
4
for subsequently performing manufacture, and to test and evaluate some test pieces obtained at the step ST
5
respectively. When a predetermined number of the test pieces satisfy the specifications in the test and evaluation step ST
6
, a step ST
7
for production is carried out. If the predetermined number of the test pieces do not satisfy the specifications at the step ST
6
, the process returns to the step ST
3
for designing the logic and/or the circuit again, for example.
FIG. 22
is a flow chart showing exemplary contents of the step ST
4
shown in FIG.
21
.
FIG. 23
is a block diagram showing an exemplary structure of the eRAM produced through the fabrication steps shown in FIG.
21
. First, blocks forming the eRAM are classified into those allowing automatic placement and routing and those allowing no automatic placement and routing respectively at a step ST
10
. As to the blocks allowing automatic placement and routing, functional blocks and standard cells are automatically arranged at a step ST
12
. Intra-block automatic routing is performed at a step ST
13
. Automatic placement and automatic routing are performed for interconnecting the blocks completing inter-block automatic routing at a step ST
14
. A computer extracts resistances and capacitances of the interconnection lines from a layout diagram thus formed (step ST
15
). Circuit simulation is performed at a step ST
16
, with addition of information of the extracted resistances and capacitances.
As to the blocks allowing no automatic placement and routing, a designer designs the layout while interacting with a layout editor (step ST
11
). The designer connects parts manually routed at the step ST
11
with those automatically placed and routed through the steps ST
12
to ST
14
, with the layout editor. The designer checks design rules at a step ST
18
. If a result of this check satisfies the specifications, the designer ascertains the layout diagram. If the specifications are not satisfied, the process returns to a proper step in response to the situations, for design the layout again.
Referring to
FIG. 23
, parts shaded with slant lines show parts allowing no automatic placement and routing, while parts of the eRAM, i.e., a CPU
120
and interconnection lines connecting the CPU
120
with banks #A to #D of a DRAM allow automatic placement and routing. In the CPU
120
consisting of a plurality of blocks, intra-block wiring and inter-block wiring are automatically performed. The parts allowing no automatic placement and routing include DRAM arrays
102
a
to
102
d
, row decoders
103
a
to
103
d
, column decoders
104
a
to
104
d
, preamplifiers/write drivers
105
a
to
105
d
, a DRAM control circuit
110
, a test circuit
140
etc.
The reason why the DRAM control circuit
110
, the test circuit
140
etc. allow no automatic placement and routing is now described with reference to the DRAM control circuit
110
. As shown in
FIG. 24
, the DRAM control circuit
110
includes an internal clock generation circuit
130
for generating various internal clocks clka to clkc from an externally supplied clock EXCLK.
FIG. 25
shows exemplary relation between the internal clocks cika to clkc and the external clock EXCLK. The DRAM must complete a series of operations within each clock EXCLK. The internal clocks clka to clkc supply the timing for the complicated series of operations progressing in a time-series manner. The interval between the internal clocks cIka to clkc, which are generated by delaying the clock EXCLK, is about several nsec. or shorter. Due to delay control for the internal clocks clka to clkc having such a short interval, it is difficult to automatically arrange/interconnection line the DRAM control circuit
110
. This also applies to the test circuit
140
generating other internal clocks.
In particular, it is difficult to set the delay time between first and second times in case of employing automatic placement and routing, although the delay time can be set within a prescribed time in the automatic placement and routing of the background technique. Referring to
FIG. 25
, the internal clock clka must be generated after a lapse of a time t
1
and before a lapse of a time t
2
, in an exemplary operation of setting the internal clock clka between first and second times.
When automatic placement and routing is employed for designing the la

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