Response resolver for associative memories and parallel processo

Details Response resolver for associative memories and parallel processo Response resolver for associative memories and parallel processo

1995-05-01

1996-02-13

Whitfield, Michael A.

Boots, shoes, and leggings

395732, 36471501, 326119, G06F 700, G06F 900, G06F 946, H03K 19094

Patent

active

054918030

ABSTRACT:
A logic circuit for a content-addressable-memory or parallel-processor array cell implements both prioritizing and counting functions for response resolution. It includes a means for receiving from a prior cell a response-resolution token and a means for receiving the positive or negative response of the current cell to a pattern to be matched. It also includes a means for deriving as a function of the prior cell's response-resolution token a response-resolution token for the current cell that implements prioritization and counting response-resolution functions for positive or negative pattern-matching responses of the current cell. Finally, it includes a means for selecting for the current cell the appropriate response-resolution token based on the cell's positive or negative pattern-matching response and a means for sending that response-resolution token to a subsequent cell. In a preferred embodiment of the invention, the means for selecting the current cell's response-resolution token for a positive or negative pattern-matching response uses a simple pass-transistor switching circuit.

REFERENCES:
patent: 3618027 (1971-11-01), Feng
patent: 4153943 (1979-05-01), Anderson
patent: 4499538 (1985-02-01), Finger et al.
patent: 4541067 (1985-09-01), Whitaker
patent: 4622648 (1986-11-01), Whitaker
patent: 4975873 (1990-12-01), Nakabayashi et al.
patent: 5325501 (1994-06-01), Carlstedt
Wade et al. "Aternary Content Addressable Search Engine" IEEE Journal of Solid-State Circuits vol. 24, No. 4, Aug. 1989 pp. 1003-1013.
Herrmann et al. "A Dynamic Associative Processor for Machine Vision applications" IEEE Micro, vol. 12, No. 3, Jun. 1992, pp. 31-41.
Anderson, G. A., "Multiple Match Resolvers: A New Design Method," IEEE Transactions on Computers, C-23, 1317-1320 (1974).
Foster, C. C., Content Addressable Parallel Processors, New York: Van Nostrand Reinhold Company, 146-167 (1976).
Foster, C. C., and Stockton, F. D., "Counting Responders in an Associative Memory," IEEE Transactions on Computers, C-20, 1580-1583 (1971).
Foster, C. C., "Determination of Priority in Associative Memories," IEEE Transactions on Computers, C-17, 788-789 (1968).
Frei, E. H., and Goldberg, J., "A Method for Resolving Multiple Responses in a Parallel Search File," IRE Transactions on Electronic Computers, EC-10, 718-722 (1961).
Kadota, H., et. al., "An 8-kbit Content-addressable and Reentrant Memory," IEEE Journal of Solid State Circuits, SC-20(5), 951-957 (1985).
Landis, D., "Multiple-response Resolution in Associative Memories," IEEE Transactions on Computers, C-26, 230-235 (1977).
Lipovski, G. J., "A Four Megabit Dynamic Systolic Associative Memory Chip," Journal of VLSI Signal Processing, 4(1), 37-51 (1992).
Lipovski, G. J., and Vaughn, P., "A Fetch-and-op Implementation for Parallel Computers," Proceedings 15th Annual Symposium on Computer Architecture, 2-10 (1988).
Miiler, H. S., "Resolving Multiple Responses in an Associative Memory," IEEE Transactions on Electronic Computers, ED-13, 614-616 (1964).
Saxton, T. L., and Huang, C. C., "An Optimal Frame Synchronization Technique Using an Associative Processor," IEEE Transactions on Computers, C-26, 170-174 (1977).
Shibuya, T., et al., "Application Specific Massively Parallel Machine," Proceedings of the Third Symposium on the Frontiers of Massively Parallel Computation, 274-277 (1990).
Weinstein, H., "Proposals for Ordered Sequential Detection of Simultaneous Multiple Responses," IEEE Transactions on Electronic Computers, EC-12, 564-567 (1963).
Yeap, T. H., et al., "Implementing the VASTOR Architecture using a VLSI Array of 1-bit Processors," IEEE International Conference on Computer Design, 494-499 (1985).

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