Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-09-10
2001-08-28
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S092000, C345S205000, C345S100000, C345S098000, C345S206000
Reexamination Certificate
active
06281865
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving circuit of a liquid crystal display device, and particularly to a driving circuit for driving signal lines.
2. Description of the Related Art
As a liquid crystal display device having a built-in driving circuit for signal lines and scan lines, there is known a device manufactured by using thin film transistors made of polysilicon.
FIG. 2
is a schematic view showing a conventional liquid crystal display device having a built-in driving circuit.
In
FIG. 2
, signal lines
206
,
207
and
208
are arranged in the row direction, scanning lines
203
,
204
and
205
are arranged in the column direction, and pixel transistors
224
and
225
are arranged in matrix at intersection points of those lines. A gate terminal of the thin film transistor
224
is connected to the scanning line
203
, a source terminal thereof is connected to the signal line
206
, and a drain terminal thereof is connected to a pixel electrode
226
.
Each of the signal lines is designed to input a video signal inputted from a video input terminal to the source terminal of the pixel transistor, and is driven by a signal line driving circuit
201
. Each of the scan lines is designed to input a scanning signal to the gate terminal of the pixel transistor and is driven by a scan line driving circuit
202
.
The signal line driving circuit
201
is constituted by a shift register
216
and analog switches
218
,
219
and
220
. This system is called dot-sequential driving, and is common in a liquid crystal display device having a built-in driving circuit.
The shift register includes an input terminal
215
for inputting a start pulse, clock input terminals
208
and
209
for sequentially shifting a pulse, and power supply terminals
213
and
214
. The outputs
221
,
222
and
223
of the shift register are connected to the analog switches
218
,
219
and
220
.
FIG. 3
shows operation waveforms of the shift register.
When clock pulses CL
1
and CL
1
b
are inputted, a start pulse is shifted according to rising and falling of the clock.
As a result, an analog switch selection pulse is outputted to the respective outputs of the shift register.
This output is inputted to the analog switches
218
,
219
and
220
, and the respective analog switches are turned on only during the period of the pulse. When the analog switch is turned on, the video line
210
,
211
, or
212
and the signal line
206
,
207
or
208
at both ends of the analog switch are short-circuited during the period, and data of the video line are written into the signal line. The data written into the signal line are inputted into pixel transistor connected to the selected scan line and are written into the pixel electrode.
The transmittance of a liquid crystal is changed by voltage between the pixel electrode and the opposite substrate so that gradation display is made.
FIGS. 4 and 5
show manufacturing steps of a conventional liquid crystal display device.
Manufacturing steps of obtaining a conventional monolithic type active matrix circuit will be described below with reference to
FIGS. 4 and 5
. The steps relate to a low temperature polysilicon process. The left sides of
FIGS. 4 and 5
show manufacturing steps of a TFT of a driving circuit and the right sides thereof show manufacturing steps of a TFT of an active matrix circuit, respectively.
First, a silicon oxide film with a thickness of 1000 to 3000 Å is formed as an underlayer oxide film
402
on a glass substrate
401
. As a method of forming the silicon oxide film, it is appropriate to use a sputtering method or a plasma CVD method in an oxygen atmosphere.
Then an amorphous silicon film with a thickness of 300 to 1500 Å, preferably 500 to 1000 Å is formed by a plasma CVD method or an LPCVD method. Then heat annealing is carried out at a temperature of 500° C. or more, preferably 500 to 600° C. to crystallize the silicon film or to raise crystallinity thereof. The crystallinity may further be raised by light (laser or the like) annealing after the crystallization by the heat annealing.
Moreover, at the crystallization by the heat annealing, an element (catalytic element) for promoting crystallization of silicon may be added as disclosed in Japanese Patent Unexamined Publication No. Hei. 6-244103 and No. Hei. 6-244104.
Next, the silicon film is etched to form an active layer
403
(for a P-channel TFT) and an active layer
404
(for an N-channel TFT) of the island-like driving circuit, and an active layer
405
of a TFT (pixel TFT) of the matrix circuit. Further, a gate insulating film of silicon oxide with a thickness of 500 to 2000 Å is formed by a sputtering method in an oxygen atmosphere. A plasma CVD method may be used for the method of forming the gate insulating film. In the case where the silicon oxide film is formed by the plasma CVD method, it was preferable to use nitrous oxide (N
2
O) or oxygen (O
2
) and monosilane (SiH
4
) as a raw material gas.
Thereafter, aluminum with a thickness of 2000 to 6000 Å is formed on the entire surface of the substrate by a sputtering method. Here, aluminum may contain silicon, scandium, palladium, or the like so as to prevent hillocks from occurring by a subsequent thermal process. This is etched to form gate electrodes
407
,
408
and
409
(FIG.
4
A).
Next, this aluminum is subjected to anodic oxidation. The surfaces of the aluminum become aluminum oxides
410
,
411
, and
412
by the anodic oxidation so that they come to have effects as insulators (FIG.
4
B).
Next, a mask
413
of photoresist covering the active layer of the P-channel TFT is formed. Then phosphorus is implanted by an ion doping method with phosphine as a doping gas. The dosage is made 1×10
12
to 5×10
13
atoms/cm
2
. As a result, high N-type regions (source, drain)
414
and
415
are formed (FIG.
4
C).
Next, a mask
416
of photoresist covering the active layer of the N-channel TFT and the active layer of the pixel TFT is formed. Then boron is implanted again by an ion doping method with diborane (B
2
H
6
) as a doping gas. The dosage is made 5×10
14
to 8×10
15
atoms/cm
2
. As a result, P-type regions
417
are formed. By the above doping steps, the high N-type regions (source, drain)
414
and
415
, and the high P-type regions (source, drain)
417
are formed (FIG.
4
D).
Thereafter, heat annealing at 450 to 850° C. for 0.5 to 3 hours is carried out to repair damages produced by doping and to activate doping impurities so that crystallinity of silicon is recovered. Then a silicon oxide film with a thickness of 3000 to 6000 Å is formed as an interlayer insulating film
418
on the entire surface by a plasma CVD method. This film may be a silicon nitride film or a multilayer film of a silicon oxide film and a silicon nitride film. Then the interlayer insulating film
418
is etched by a wet etching method or a dry etching method to form contact holes to the source/drain.
Then an aluminum film or a multilayer film of titanium and aluminum with a thickness of 2000 to 6000 Å is formed by a sputtering method. This film is etched to form electrode/wiring lines
419
,
420
, and
421
of the peripheral circuit and electrode/wiring lines
422
and
423
of the pixel TFT (FIG.
5
E).
Further, polyimide with a thickness of 10000 Å is applied to form a second interlayer film
424
. Next, titanium with a thickness of 2000 to 3000 Å is formed and is etched to form a black matrix
426
on the TFT. Further, polyimide with a thickness of 5000 to 6000 Å is applied to form a third interlayer film. Next, the second and third interlayer films are etched to form a contact hole reaching the electrode
423
of the TFT. Finally, an ITO (indium-tin oxide) film formed by a sputtering method and having a thickness of 500 to 1500 Å is etched to form a pixel electrode
425
. In this way, the peripheral driving circuit and the active matrix circuit are integrally formed (FIG.
5
F).
FIG. 6
shows a patt
Koyama Jun
Kubota Yasushi
Sakai Tamotsu
Tanaka Yukio
Hjerpe Richard
Nixon & Peabody LLP
Robinson Eric J.
Semiconductor Energy Laboratory Co,. Ltd.
Zamani Ali
LandOfFree
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