Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
2000-01-28
2001-07-10
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S175000, C327S263000, C327S271000, C327S291000, C365S233500
Reexamination Certificate
active
06259283
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to integrated circuits (ICs). More particularly, the invention relates to a clock doubler circuit and method for an IC.
BACKGROUND OF THE INVENTION
Clock signals are used in virtually every IC and electronic system to control timing. For example, every time there is a rising edge on a clock signal, all the flip-flops in a circuit may change state. Clearly, the higher the frequency of the clock signal, the faster the circuit operates. Therefore, where performance is an issue, circuit designers usually prefer to use the fastest available clock that can be supported by the delays on the logic paths through the circuit. In other words, the performance of a circuit is typically limited by the logic delays on the slowest logic path. However, sometimes the longest path delay through the circuit is significantly shorter than the period of the available clock, and the frequency of the available clock becomes the limiting factor.
To overcome this limitation, circuit designers can double the frequency of a clock signal using a phase-lock loop (PLL) or delay-lock loop (DLL) circuit. However, PLL and DLL circuits consume a great deal of silicon area. Additionally, PLLs are often analog in nature and take an extremely long time to simulate, and a design that works in one manufacturing process may stop working when manufactured using another process. Therefore, PLLs are very difficult to design, and often are not feasible in a given circuit or system. DLLs are also very complicated and difficult to design. Therefore, clock doubling is often not feasible using known circuits and methods.
Therefore, it is desirable to provide a circuit and method that enables a circuit designer to double the frequency of an input clock without using a PLL or DLL, using a fairly simple circuit that consumes a relatively small amount of silicon area.
SUMMARY OF THE INVENTION
The invention provides a clock doubler circuit and method that accept an input clock signal and provide therefrom an output clock signal having a frequency twice that of the input clock signal. One circuit according to the invention includes an input clock terminal supplying an input clock signal, and a delay line driven by the input clock signal and supplying a plurality of intermediate clock signals delayed from the input clock signal by incremental unit delays. A clock multiplexer selects from among these intermediate clock signals, under control of a multiplexer control circuit, the clock signal that is most nearly 90 degrees offset from the input clock, i.e., the clock signal subject to a delay about equal to half of one input clock pulse (e.g., closest to but not exceeding half of one high pulse). The input clock signal is appropriately delayed to compensate for the delay through the clock multiplexer, then combined with the selected clock signal in an output clock generator that provides an output clock signal having a frequency twice that of the input clock signal. (In another embodiment, the intermediate clock signal selected by the clock multiplexer is the intermediate clock signal subject to a delay closest to and exceeding half of one input clock pulse.)
The multiplexer control circuit essentially counts the number of unit delays between first (e.g., rising) and second (e.g., falling) edges of the input clock signal. This total number of unit delays is divided by two, thus supplying the desired number of unit delays required to delay the input clock signal by 90 degrees. This number is used to select the correct intermediate clock signal, e.g., the clock signal subject to a delay closest to but not exceeding half of one input clock pulse.
Note that in order to obtain a symmetrical output clock signal, a symmetrical input clock signal is required; i.e., a clock signal having high and low pulses of about equal duration. An asymmetrical input clock signal results in an asymmetrical output clock signal, and in extreme cases (e.g., where half the high pulse is longer than the low pulse) the circuit does not function properly.
In one embodiment, the clock doubler circuit includes an option to disable the circuit. A disable control signal is applied to the output clock generator to select the input clock signal as the output clock signal. Therefore, no clock doubling is performed.
In another embodiment, the clock doubler circuit includes a preliminary delay stage for the delay line. The preliminary stage comprises a delay element that can selectively add either a full unit delay or a half-unit delay to the input clock signal. Using this additional delay element, the clock doubler circuit can supply a clock more nearly offset by 90 degrees. If the clock pulse spans an odd number of unit delays, the half-unit delay is inserted. If the clock pulse spans an even number of unit delays, a full unit delay is inserted, and the circuit operates as described above. In other embodiments, rather than adding a selectable half/full unit delay element at the beginning of the delay line, the first stage of the delay line is modified to offer a half/full unit delay option, or a full/one-and-a-half unit delay option. As long as corresponding changes are made to the select generation circuitry, as is easily done by those of ordinary skill in the art, any of these or similar changes to the delay line are easily accommodated by the circuits and methods of the invention.
In yet another embodiment, a status generator circuit is provided that provides a status signal after a predetermined number of clock cycles have elapsed. This status signal may be used by other circuits to disable the output clock signal until the output clock signal has settled into a reliably predictable pattern.
An advantage of the invention is that the output clock is always in synchronization with the input clock. Because in the described embodiments the rising edge of the input clock always triggers a rising edge of the output clock, two periods of the output clock are always equivalent to one period of the input clock. There can be no “creeping” (i.e., no offset that increases over time) of the output clock with respect to the input clock.
Another advantage of the invention is that the circuit of the invention can be cascaded, allowing the generation of a 4X clock, an 8X clock, and so forth.
REFERENCES:
patent: 5245637 (1993-09-01), Gersbach et al.
patent: 5537069 (1996-07-01), Volk
patent: 5994938 (1999-11-01), Lesmeister
patent: 6040726 (2000-03-01), Martin
patent: 6100735 (2000-08-01), Lu
Xilinx Application Note, “Using the Virtex Delay-Locked Loop”, XAPP132, Oct. 21 1998 (Version 1.31).
Callahan Timothy P.
Cartier Lois D.
Nguyen Minh
Xilinx , Inc.
LandOfFree
Clock doubler circuit and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clock doubler circuit and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock doubler circuit and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2464849