Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
1999-12-13
2001-01-30
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S778000, C257S777000, C257S723000, C257S784000, C257S738000
Reexamination Certificate
active
06181002
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a resin overmolded type semiconductor device having a plurality of semiconductor chips arranged therein in a stacked relation for higher density integration.
2. Description of the Related Art
For enhancement of the capacities and additional values of memories for portable systems and the like, semiconductor devices have been provided which include a plurality of semiconductor chips mounted in a single package. One example of such semiconductor devices is a multi-chip module in which a plurality of semiconductor chips are arranged in juxtaposition. However, the juxtaposition of the semiconductor chips makes it impossible to fabricate a package having a smaller plan surface area than the total plan surface area of the mounted semiconductor chips.
Another example of the aforesaid semiconductor devices includes a package in which a plurality of semiconductor chips are arranged in a stacked relation for higher density integration (hereinafter referred to as “stacked package”).
One exemplary stacked package is a chip size package (hereinafter referred to as “CSP”) having such a construction that semiconductor chips are stacked on an electrically insulative substrate which has external connection terminals arranged in a matrix array on its back surface.
FIG. 5
is a sectional view illustrating a semiconductor device of the CSP structure. Where the semiconductor device shown in
FIG. 5
includes semiconductor chips of different plan surface areas arranged therein in a stacked relation, the outer size of a package of the semiconductor device depends on the size of a semiconductor chip having the largest plan surface area. In the case of the conventional semiconductor device, no consideration is given to the thicknesses of the respective semiconductor chips, that is, the semiconductor chips typically have the same thickness. Since the stacked package contains therein a chip having a smaller plan surface area unlike a single chip package of the CSP structure as shown in
FIG. 6
, the semiconductor chips occupy a smaller proportion of the volume of the stacked package than a molded resin portion.
The aforesaid semiconductor device has a small size with its external connection terminals being arranged in an area array. The semiconductor device having such a construction is mounted on a printed board by are flow process. The package of the semiconductor device may be of a BGA (ball grid array) structure with the external terminals being formedas solder balls, or of aLGA (landgridarray) structure with the external terminals being formed of a solder paste as trapezoidal lands.
If a temperature change occurs in the semiconductor device and the printed board due to a heat cycle or the like after the reflow process for the mounting, the semiconductor device may warp, and stresses may occur in junctures between the semiconductor device and the printed board due to a difference in the coefficient of linear expansion therebetween.
In the aforesaid semiconductor device, only one side of the semiconductor chip is sealed with a mold resin. Therefore, the temperature change causes the semiconductor device to warp as shown in
FIG. 7
due to a so-called bimetal phenomenon occurring between the semiconductor chip and the mold resin portion. The warpage of the semiconductor device causes stresses in the junctures between the semiconductor device and the printed board, resulting in cracking and breakage of the junctures.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a semiconductor device which comprises: an insulative substrate having a layer of interconnection patterns formedonachip-side surface thereof, and external terminals formed on a surface thereof opposite from the chip-side surface; and a plurality of semiconductor chips stacked on the chip-side surface of the insulative substrate and electrically connected to the corresponding interconnection patterns; wherein, among the plurality of semiconductor chips, a semiconductor chip having the largest plan surface area has the greatest thickness.
In the semiconductor device, another layer of interconnection patterns is provided on the surface of the insulative substrate opposite from the chip-side surface.
REFERENCES:
patent: 5773896 (1998-06-01), Fugimoto et al.
patent: 5804004 (1998-09-01), Tuckerman et al.
patent: 5861666 (1999-01-01), Bellaar
patent: 5953588 (1999-09-01), Camien et al.
patent: 0782191A2 (1997-07-01), None
patent: 9-186289 (1997-07-01), None
Juso Hiroyuki
Maruyama Tomoyo
Sota Yoshiki
Nixon & Vanderhye PC
Parekh Nitin
Sharp Kabushiki Kaisha
Thomas Tom
LandOfFree
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