Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal
Reexamination Certificate
1998-06-04
2001-08-07
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Frequency or phase control using synchronizing signal
C375S369000, C370S514000, C370S522000
Reexamination Certificate
active
06272194
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a synchronization signal detecting circuit and a method employed by the circuit. More particularly, the invention relates to a circuit and method for detecting a sync pattern in a bit stream such as a Moving Picture Coding Experts Group (“MPEG”) audio bit stream. Also, the present invention relates to a program which causes a processor to execute the method for detecting the sync pattern and relates to an information storage medium for storing the program.
BACKGROUND OF THE INVENTION
In many communication and entertainment systems, the systems receive and process data contained in a bit stream. In order to synchronize the operations of the systems with the data in the bit stream, the systems must detect a sync pattern contained in the bit stream to determine the beginning of a particular segment (i.e. frame) contained in the bit stream.
FIG. 3
illustrates an example of a bit stream of a digital signal such as MPEG audio bit stream. As shown in the figure, the bit stream is divided into a plurality of sequential frames, and each of the frames contains a header portion, an audio data portion, and an ancillary data portion. Also, each of the frames in the MPEG audio bit stream has the same length.
The header portion comprises a sync pattern followed by coded data. If the MPEG audio bit stream follows the standard set by the International Standardization Organization/ International Electrotechnical Commission (“ISO/IEC”) 11172-3, the sync pattern is defined by a series of 12 bits having a logic value equal to “1” (i.e. “111111111111”). Also, the coded data following the sync pattern comprises 20 bits of data which indicate characteristics of the bit stream or frame. For example, the coded data may indicate the length of the frames in the bit stream or the particular format of the data in the bit stream.
The audio data portion contains audio data (e.g. data needed to reproducing a song) transmitted in the bit stream. Also, the ancillary data portion contains ancillary data that may be generated at the transmission source of the bit stream. The ancillary data may indicate the titles of the songs contained in the audio data portion and/or the names of the singers which sing the songs.
An apparatus which processes the data contained in an MPEG audio bit stream to reproduce an audio signal corresponding to the audio data contains a synchronization detecting circuit for detecting the sync pattern. After the timing of the sync pattern is determined, the apparatus can accurately locate and process the coded data and audio data to reproduce the audio signal.
However, since many types of ancillary data may potentially be contained in the ancillary data portion of the bit stream, a significant possibility exists that a series of 12 bits having a logic value equal to “1” (i.e. “111111111111”) is contained in the ancillary data portion. In order to avoid erroneously identifying a particular data pattern “111111111111” in the ancillary data portion as the sync pattern, the synchronization detection circuit determines if another data pattern “111111111111” is separated from the particular data pattern “111111111111” by the period of one frame of the bit stream. In other words, since the beginning of the sync pattern is located at the first bit in each frame and since each frame in the MPEG audio bit stream is the same length, the detection circuit assumes that two data patterns “111111111111” separated by the period of a frame are sync patterns.
However, since various types of data are stored in the ancillary data portion of a frame, a significant possibility exists that data patterns “111111111111” will be respectively contained in the same positions in the ancillary data portions of sequential frames. For example, as mentioned above, the title of a song may be stored in the ancillary data portion, and it may be repeated in a plurality of frames to enable the title to be easily read by a reproducing apparatus. Therefore, if the data representing the title of the song contains the data pattern “111111111111”, such data pattern “111111111111” will likely be repeated at the same locations in the ancillary data portions of sequential frames. Thus, they will be separated by a period of one frame, and the conventional synchronization detection circuit will erroneously detect the data relating to the title of the song as a sync pattern.
FIG. 4
illustrates a bit stream in which a data pattern “111111111111” is repeatedly contained in the ancillary data portion of sequential frames. In particular, the bit stream contains a three sequential frames
70
,
80
, and
90
, which respectively have sync patterns
100
,
102
, and
104
. Also, the ancillary data portions of the frames
70
,
80
, and
90
, contain the data patterns “111111111111”
200
,
202
, and
204
. Also, the data patterns “111111111111”
200
,
202
, and
204
are located at the same bit position in each of the ancillary data portions, and thus, they are separated by a period of one frame. Thus, the data patterns “111111111111” will likely be erroneously detected as a sync pattern.
As described above, a substantial possibility exists that data patterns “11111111111” may be separated by a period of one frame but may not be sync patterns. In such case, a synchronization detection circuit may erroneously recognize such data patterns “111111111111” as sync patterns. When the synchronization of the apparatus is established based on the erroneous data patterns “111111111111”, the apparatus is not capable of properly reproducing the audio data contained in the audio data portion of the frame, and noise is produced.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a data processing apparatus and method which are capable of correctly detecting a sync pattern in a bit stream even if a data pattern that is identical to the sync pattern is recorded in an ancillary data portion in a frame of a bit stream.
In order to achieve the above and other objects, an apparatus for detecting data in a bit stream is provided. The bit stream contains a sequence of frames, and each frame has a predetermined number of bits and comprises a sync pattern and a data portion. The apparatus comprises: a detecting circuit which detects a first data pattern in said bit stream that equals said sync pattern and detects a second data pattern in said bit stream that equals said sync pattern; a counting circuit operably coupled to said detecting circuit, wherein said counting circuit begins counting bits in said bit stream to generate a count value when said first data pattern is detected by said detection circuit; and a synchronization signal generating circuit operably connected to said counting circuit, wherein said synchronization signal generating circuit receives said count value from said counting circuit and compares said count value with a predetermined value when said second data pattern is detected by said detecting circuit, wherein said synchronization signal generating circuit outputs a synchronization signal when said count value and said predetermined value have a predetermined relationship.
In order to further achieve the above and other objects, a method for detecting data in a bit stream is provided. The bit stream contains a sequence of frames, and each frame has a predetermined number of bits and comprises a sync pattern and a data portion. The method comprises the steps of: (a) inputting said bit stream; (b) detecting a first data pattern in said bit stream that equals said sync pattern; (c) detecting a second data pattern in said bit stream that equals said sync pattern; (d) generating a count value by beginning to count bits in said bit stream when said first data pattern is detected; and (e) comparing said count value with a predetermined value when said second data pattern is detected and outputting a synchronization signal when said count value and said predetermined value have a predetermined relationship.
In order to additionally achieve the above and other objects, an
Chin Stephen
Ghayour Mohammad
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
LandOfFree
Synchronous signal detecting circuit, method, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Synchronous signal detecting circuit, method, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous signal detecting circuit, method, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2462252