Structure and fabrication method for multiple crown capacitor

Details Structure and fabrication method for multiple crown capacitor Structure and fabrication method for multiple crown capacitor

1999-08-10

2001-01-30

Loke, Steven (Department: 2811)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S397000, C438S398000, C438S253000, C438S354000, C438S255000, C257S306000

Reexamination Certificate

active

06180483

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 88109187, filed Jun. 3, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure and a fabrication method for a semiconductor device. More particularly, the present invention relates to a structure and a fabrication method for a multiple crown capacitor in a dynamic random access memory (DRAM) cell.
2. Description of the Related Art
The capacitor is the center for signal storage in a DRAM cell. As the amount of charge being stored by the capacitor is increased, the effect of noise on the information reading, such as soft errors induced by the a particles, and the refresh frequency are greatly reduced.
Increasing the charge storage capacity of a capacitor is generally accomplished by the following methods. Substituting the dielectric layer with a high dielectric constant material increases the charge storage capacity per unit area of the capacitor. Reducing the thickness of the dielectric layer also increases the capacitance of the capacitor. The material properties of the dielectric layer and the current manufacturing technique, however, require a minimum thickness of dielectric layer. Increasing the surface area of the capacitor increases the amount of charge being stored in the capacitor; however, this also lowers the integration of a DRAM device.
The charge storage capacity for a traditional DRAM cell is normally low because a two dimensional capacitor, in another words, the planar-type capacitor, is used in the manufacturing of the integrated circuits. The planar-type capacitor occupies a great amount of the area in the semiconductor substrate designated for charge storage, and is thus not suitable for the design of a highly integrated device. A three dimensional capacitor is required for the highly integrated DRAM cell such as the stacked-type, the trench-type and the crown-type capacitor. As the memory device enters an even higher level of integration, especially in DRAM cells of 64Mb and beyond, however, a simple three dimensional capacitor structure is still not adequate. Hence, methods of increasing the surface area of a dynamic random access memory cell capacitor within a small area are being developed.
SUMMARY OF THE INVENTION
The current invention provides a fabrication method of a multiple crown capacitor for a DRAM cell, which is applicable to a substrate comprising an isolation layer with a node contact plug. This method includes forming a sacrificial layer on the substrate, followed by patterning the sacrificial layer. A succession of openings is formed above the node contact plug and surrounding the node contact plug, exposing the isolation layer and a portion of the node contact plug upper surface. A conformal conductive layer is formed on the patterned sacrificial layer and in the openings. A portion of the conductive layer, which is higher than the sacrificial layer, is removed, followed by removing the sacrificial layer to convert the conductive layer to a multiple crown bottom electrode. A conformal dielectric layer and the upper electrode are then sequentially formed on the bottom electrode to complete the manufacturing of the capacitor.
The present invention further provides a structure of a multiple crown capacitor, which can be used in a DRAM cell device. The structure comprises a substrate with an isolation layer and a node contact plug formed in the isolation layer. A bottom electrode with a succession of openings is formed above the node contact plug and is electrically connected to the node contact plug. A conformal dielectric layer and an upper electrode are sequentially formed on the bottom electrode.
According to the present invention, only one sacrificial layer mask needs to be patterned to complete the manufacturing of the entire capacitor. The manufacturing process of the present invention is not only simple; the resulting capacitor also comprises a greater surface area.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5279983 (1994-01-01), Ahn
patent: 5364809 (1994-11-01), Kwon et al.
patent: 5854105 (1998-12-01), Tseng
patent: 5933742 (1999-08-01), Wu
patent: 6087216 (2000-07-01), Wang

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