Reference type input first stage circuit in a semiconductor...

Details Reference type input first stage circuit in a semiconductor... Reference type input first stage circuit in a semiconductor...

1999-04-30

2001-04-10

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S069000, C327S074000, C327S403000

Reexamination Certificate

active

06215336

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and method of forming the same, and more particularly to a reference type input first stage circuit in a semiconductor integrated circuit and a method of forming the same.
In recent years, the requirement for improvement in high speed performance of the semiconductor memory device has been on the increase. In response to the above requirement, a reference type input first stage circuit has been used in place of an invertor type first stage circuit. The reference type input first stage circuit is capable of shortening an operating time by about 1 nanosecond as compared to the invertor type first stage circuit.
FIG. 1
is a circuit diagram illustrative of a first conventional reference type first stage circuit. The first conventional reference type first stage circuit comprises first and second invertor circuits. The first invertor circuit comprises a series connection of a first transistor Q
31
and a third transistor Q
33
between a high voltage line and a ground line. The first transistor Q
31
is connected to the high voltage line, whilst the third transistor Q
33
is connected to the ground line. The second invertor circuit also comprises a series connection of a second transistor Q
32
and a fourth transistor Q
34
between the high voltage line and the ground line. The second transistor Q
32
is connected to the high voltage line, whilst the fourth transistor Q
34
is connected to the ground line. The first conventional reference type first stage circuit also has a reference voltage input terminal InR
3
which is connected to a gate of the third transistor Q
33
as well as a signal input terminal In
3
which is connected to a gate of the fourth transistor Q
34
. Gates of the first and second transistors Q
31
and Q
32
are connected in series to each other through a first node. A gate of the first transistor Q
31
is connected to a gate of the second transistor Q
32
through a second node. The first node is also connected to the second node. The second and fourth transistors Q
32
and Q
34
are connected in series to each other through an output node which is connected to an output terminal Out
3
. The first and second transistors Q
31
and Q
32
comprise p-channel MOS field effect transistors, whilst the third and fourth transistors Q
33
and Q
34
comprise n-channel MOS field effect transistors.
The above reference type input first stage circuit has the following advantages as compared to the invertor type input first stage circuit. The first advantage is that the reference type input first stage circuit is superior in high speed performance as compared to the invertor type input first stage circuit. The second advantage is that it is easy to change a first stage characteristic (VIH/VIL) by changing a reference voltage level Vref as inputted into the reference voltage input terminal, wherein “VIH” means a point where the output node connected to the next stage is changed from high level to low level upon sensing of the high level by the first stage when the input signal is changed in level from the low level to the high level, whilst “VIL” means a point where the output node connected to the next stage is changed from low level to high level upon sensing of the low level by the first stage when the input signal is changed in level from the high level to the low level.
The reference type input first stage circuit superior in high speed performances is so sensitive that the first stage characteristic (VIH/VIL) is variable by influences of noises or level shift on a power voltage level Vdd and a ground level. Those level shifts depend upon actual layouts, for example, distances from individual pads, and influences by operations of other circuit near the first stage circuit.
FIG. 2
is a circuit diagram illustrative of a conventional circuit comprising first and second reference type input first stage circuits “A” and “B”. The first reference type first stage circuit “A” comprises first and second invertor circuits. The first invertor circuit comprises a series connection of a first transistor Q
41
and a third transistor Q
43
between a high voltage line and a ground pad
6
. The first transistor Q
41
is connected to the high voltage line, whilst the third transistor Q
43
is connected through a first ground pad resistance Rg
1
to the ground pad
6
. The second invertor circuit also comprises a series connection of a second transistor Q
42
and a fourth transistor Q
44
between the high voltage line and the ground line. The second transistor Q
42
is connected to the high voltage line, whilst the fourth transistor Q
44
is connected through the first ground pad resistance Rg
1
to the ground pad
6
. The first reference type first stage circuit is connected to a reference voltage generating circuit
1
which is connected through a series connection of first and second resistances R
11
and R
12
to the ground line. An intermediate point between the first and second resistances R
11
and R
12
is connected to a gate of the third transistor Q
43
for applying a reference voltage Vref to the gate of the third transistor Q
43
. The first reference type input first stage circuit has a signal input terminal In
1
which is connected to a gate of the fourth transistor Q
44
. Gates of the first and second transistors Q
41
and Q
42
are connected in series to each other through a first node. A gate of the first transistor Q
41
is connected to a gate of the second transistor Q
42
through a second node. The first node is also connected to the second node. The second and fourth transistors Q
42
and Q
44
are connected in series to each other through an output node which is connected to an output terminal Out
1
. The first and second transistors Q
41
and Q
42
comprise p-channel MOS field effect transistors, whilst the third and fourth transistors Q
43
and Q
44
comprise n-channel MOS field effect transistors.
The second reference type first stage circuit “B” comprises first and second invertor circuits. The first invertor circuit comprises a series connection of a first transistor Q
51
and a third transistor Q
53
between a high voltage line and the ground pad
6
. The first transistor Q
51
is connected to the high voltage line, whilst the third transistor Q
53
is connected through the first ground pad resistance Rg
1
and a second ground pad resistance Rg
2
to the ground pad
6
. The second invertor circuit also comprises a series connection of a second transistor Q
52
and a fourth transistor Q
54
between the high voltage line and the ground pad
6
. The second transistor Q
52
is connected to the high voltage line, whilst the fourth transistor Q
54
is connected through the first ground pad resistance Rg
1
and the second ground pad resistance Rg
2
to the ground pad
6
. The second reference type first stage circuit is also connected to the reference voltage generating circuit
1
which is connected through the series connection of the first and second resistances R
11
and R
12
to the ground line. The intermediate point between the first and second resistances R
11
and R
12
is connected to a gate of the third transistor Q
53
for applying a reference voltage Vref to the gate of the third transistor Q
53
. The reference type input first stage circuit has a signal input terminal In
2
which is connected to a gate of the fourth transistor Q
54
. Gates of the first and second transistors Q
51
and Q
52
are connected in series to each other through a first node. A gate of the first transistor Q
51
is connected to a gate of the second transistor Q
52
through a second node. The first node is also connected to the second node. The second and fourth transistors Q
52
and Q
54
are connected in series to each other through an output node which is connected to an output terminal Out
2
. The first and second transistors Q
51
and Q
52
comprise p-channel MOS field effect transistors, whilst the third and fourth transistors Q
53
and Q
54
comprise n-channel MOS field effect trans

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