Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-01-31
2001-07-03
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S432000, C438S431000, C438S435000
Reexamination Certificate
active
06255193
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the field of semiconductor technology and semiconductor manufacture.
Isolation trenches are frequently used in integrated circuits in order to insulate neighboring active zones or switching elements from one another. Such trenches, which are arranged in the semiconductor substrate and filled with an insulation material, may have different lateral and vertical dimensions depending on the boundary conditions given. Their surface generally terminates with that of the semiconductor substrate, this being achieved by means of a suitable planarization process. One problem with the use of such isolation trenches is that the trench etching causes crystal damage. Such crystal damage very often has negative consequences for the circuit to be fabricated, owing to the fact that, by way of example, the diffusion of impurity atoms is facilitated or the crystal structure of subsequently applied layers is deleteriously affected.
Although it is generally applicable, the problem underlying the invention is explained using a DRAM memory circuit with trench capacitors. In order to isolate neighboring memory cells, the so-called STI technique (Shallow Trench Isolation) is frequently employed. In the context of memory cells with trench capacitors, this is done, in particular, by means of an arrangement of the isolation trench which partly overlaps two capacitors in each case. In this case, first of all the capacitor trenches are fabricated and filled and then an isolation trench is etched in such a way that it partly covers the upper region of two neighboring trenches.
A conventional prior art method for fabricating the isolation trench is explained with reference to
FIGS. 4
to
5
. The capacitor trenches
2
,
3
of mutually adjacent memory cells are completed in a semiconductor substrate
1
. The trench wall is lined with a capacitor dielectric
4
in the lower region and with an insulation collar
5
made of silicon oxide, which is thicker by comparison with the dielectric liner
4
, in the upper region. The insulation collar
5
can be removed in the vicinity of the upper edge of the trenches, in order to enable here the subsequent contact with the selection transistor of the cell. The capacitor trench is filled with polysilicon
6
, which bears on the trench wall in the vicinity of the upper edge of the trenches. An isolation trench
7
is etched in such a way that the substrate located between the capacitor trenches
2
,
3
and that part of the capacitor trenches which adjoins the substrate are covered. A mask for etching the isolation trench covers at least the active zone of the substrate. The trench, i.e., the STI trench, is etched down to a predetermined depth, in this case at least down to the insulation collar
5
.
The etching of this STI trench causes damage in the substrate. The damage must be minimized, since the selection transistor of the memory cell is fabricated in the relevant substrate region following the capacitor trench. Annealing is effected by an oxidation process (furnace process or RTP), as a result of which a so-called “liner oxide”
8
is formed on the side wall and the bottom of the isolation trench
7
. The liner oxide
8
additionally improves lattice matching during the filling of the isolation trench. The isolation trench is filled with an insulation layer
10
.
During subsequent oxidation steps in the process (and to a small extent already during the oxidative annealing), however, structures located at a deeper level may also be oxidized, in particular the insulation collar
5
is oxidized further (see FIG.
2
). As a result, there is the risk of crystal defects being formed in the substrate, which adversely affect the electrical properties of the memory cell (for example alternation of the retention time, so-called variable retention time) or lead to complete failure of the cell.
This problem has been countered heretofore by a thin nitride layer as an oxygen barrier on the liner oxide
8
. The use of such a nitride layer is not without problems, however, since the lattice matching is not optimal and stresses may be produced. Furthermore, an additional furnace deposition is necessary.
SUMMARY OF THE INVENTION
The object of the invention is to provide a method for fabricating an isolation trench which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which, in particular, avoids the oxidation of lower-lying structures.
With the above and other objects in view there is provided, in accordance with the invention, a method for fabricating an isolation trench in a semiconductor structure, which comprises the following steps:
producing a trench in a semiconductor substrate;
forming an oxidizable auxiliary layer; and
filling the trench with an insulation layer.
In other words, the invention is based on the use of an oxidizable auxiliary layer before the trench is filled with an insulation layer. This auxiliary layer consumes the diffusing oxygen during subsequent process steps. The oxidation of deeper structures, for example of an insulation collar of a trench capacitor, is thereby considerably delayed or prevented.
A silicon layer or silicon oxide high in silicon is particularly suitable as the auxiliary layer. The silicon oxide is then completely converted into silicon oxide.
The auxiliary layer may be fabricated in a separate step. It is particularly advantageous, however, for its fabrication to precede directly (in situ) the fabrication of the trench filling. In other words, first the auxiliary layer is deposited and then the insulation layer for filling the trench is deposited, in the same installation without the substrate being exposed to the surrounding atmosphere in the meantime, preferably in the same process chamber. This can be achieved by switching on the participating process gases in a manner that is staggered over time, and/or by changing the relative ratio of the process gases in the overall gas mixture.
In accordance with another feature of the invention, the surface is planarized after the trench has been filled.
In accordance with a further feature of the invention, the trench is etched in an overlapping manner with a capacitor trench in the substrate. A wall of the capacitor trench is at least partly covered with silicon oxide and the capacitor trench is filled with a conductive material.
In accordance with a concomitant feature of the invention, the trench is lined with a thermal oxide prior to the formation of the oxidizable auxiliary layer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating an isolation trench using an auxiliary layer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5047815 (1991-09-01), Yashuhira et al.
patent: 5358891 (1994-10-01), Tsang et al.
patent: 5867420 (1999-08-01), Alsmeier
patent: 5869384 (1999-02-01), Yu et al.
patent: 5933748 (1999-08-01), Chou et al.
patent: 8-70108 (0000-01-01), None
patent: 10-125770 (0000-01-01), None
Sperlich Hans-Peter
Zimmermann Jens
Dang Trung
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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