Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
1995-11-14
2001-03-20
Banankhah, Majid (Department: 2755)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
Reexamination Certificate
active
06205467
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of microprocessors and, more particularly, to context saving mechanisms and interrupt handling within microprocessors.
2. Description of the Relevant Art
Modern computer systems and the software which runs thereon demand a high performance interrupt structure in order to operate efficiently. Interrupts are used to switch between tasks, and so a multi-tasking operating system benefits from a high performance interrupt structure. A “multi-tasking” operating system is configured to run multiple programs concurrently. Additionally, interrupts provide a means for an electronic device external to the microprocessor to request attention from the operating system. Modern day computer systems are including increasing numbers of these electronic devices, prompting the need for a high performance interrupt structure.
Interrupts cause a microprocessor within the computer system to execute a specific software routine (referred to as an interrupt service routine) comprising a set of instructions. The interrupt is typically unrelated to the instructions being executed by the microprocessor. Instead, the interrupt is caused by an external device requiring software attention. For example, a buffer within an input/output device may fill with data to be transferred to another device or to memory. Many other sources for interrupts are well-known to the skilled artisan.
The instructions being executed by the microprocessor at the time the interrupt occurs are referred to herein as a “task”. A task may be a portion of a program, an operating system routine, or even another interrupt service routine. The interrupt service routine is stored in memory at an address indicated by an interrupt vector associated with the interrupt.
Because the interrupt is normally unrelated to the task being performed by the microprocessor and is asynchronous to the task itself, the interrupt service routine is executed in such a way that the task may be resumed. In order to resume the task, the “context” within which the task is executing is saved to memory. The context includes register values associated with the task when the task is interrupted. Additionally, the context includes the values within any memory locations that may be accessible to the task. The register portion of the context is saved to memory, and the memory locations are saved by causing the current values stored therein to be visible to the computer system. For example, memory locations are saved if stored into a data cache and the data cache is maintained coherent with main memory. After saving the context, the interrupt service routine is executed. Upon completion of the interrupt service routine, the context is restored to the microprocessor and the task is resumed. Since the restored context is identical to the context when the task was interrupted, the task executes normally. In other words, the interrupt had no effect on the result of executing the task if the task is unrelated to the interrupt. Instead, only the time required to execute the task is affected.
The memory locations in which the context is saved, referred to herein as a context storage location, are typically indicated by an address stored in a register or a data structure. The microprocessor architecture implemented by the microprocessor may specify where and how the context storage location is located. Conversely, the particular operating system running on the computer system employing the microprocessor may determine where and how the context storage location is located. For example, a microprocessor employing the x86 microprocessor architecture includes a task register which identifies the address in memory in which the current context is to be stored. Included in the context storage location is a value which indicates the origin of the task as well as many of the registers defined by the x86 architecture. The origin of a particular task may be another task which invoked the particular task, for example. More information regarding the interrupt structure and the context stored in the x86 architecture may be found in the publication entitled: “PC Magazine Programmer's Technical Reference: The Processor and Coprocessor” by Robert L. Hummel, Ziff-Davis Press, Emeryville, Calif., 1992. This publication is incorporated herein by reference in its entirety.
The x86 architecture defines the context of 32 bit microprocessors to be 68 bytes. Additionally, when the segment registers (which are part of the context in the x86 architecture) are reloaded, segment reloads are initiated to translate the segments. More bytes are transferred when the reload occurs, and clock cycles are required to translate the extra bytes into a format for storing within the microprocessor.
Unfortunately, storing a large number of bytes to memory (as a context save entails) often requires a relatively large number of clock cycles. A clock cycle refers to the amount of time required by portions of the microprocessor to perform their functions. At the end of the clock cycle, the results of each function are stored in a storage location (e.g. a register or memory) and may be used by another function in the next clock cycle. The bus used by a microprocessor to communicate with other electrical devices may operate according to a different clock cycle than the microprocessor itself. The clock cycle associated with the bus is often referred to as the bus clock cycle.
If the context is saved by the microprocessor when an interrupt is recognized by the microprocessor, the interrupt is being handled via a “task switch”. The interrupt service routine is isolated from the interrupted task such that any modifications the interrupt service routine performs to the microprocessor's context information will not affect the operation of the task when resumed. The context is restored prior to resuming the task. Often, an interrupt service routine will only require access to a few registers within the register set to perform its function. In this case, a full context save is not necessary since some registers will not be modified by the interrupt service routine. Instead, only those storage locations which must be changed in order to fetch the instructions within the interrupt service routine need be saved prior to beginning execution of the interrupt service routine. For example, in the x86 architecture the EIP register and CS segment register (which define the address and segment of the instructions to be fetched and executed) and the flags register (which is modified by many of the x86 instructions) are saved. These values are pushed onto the stack defined by the x86 architecture when not using the task switch method of interrupt handling.
When the task switch method of interrupt handling is not in use, an interrupt service routine must save the values stored within registers which it employs to carry out its intended function. Often, the values are stored on the stack. This method of interrupt handling is referred to as an interrupt gate or trap gate in the x86 architecture, depending on whether or not the interrupt service routine may itself be interrupted. If the interrupt service routine does not use all of the microprocessor's context, then clock cycles may be saved with respect to performing the full context save of a task switch. The interrupt service routine is entered and exited more rapidly since context save and restore is not performed. Unfortunately, at least a few registers must still be stored. Additionally, the instruction code required to store the registers and restore them at the completion of the routine lengthens the corresponding interrupt service routine. Furthermore, an administrative burden is placed upon the programmer of the interrupt service routine to update instruction code for saving and restoring registers when the interrupt service routine is changed. An interrupt handling mechanism for a microprocessor which rapidly switches from a task to an interrupt handler without applying the burdens
Barnes Brian C.
Lambrecht J. Andrew
Advanced Micro Devices , Inc.
Banankhah Majid
Conley Rose & Tayon PC
Kowert Robert C.
Merkel Lawrence J.
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