Test system with mechanical alignment for semiconductor chip...

Details Test system with mechanical alignment for semiconductor chip... Test system with mechanical alignment for semiconductor chip...

1999-08-02

2001-05-08

Nguyen, Vinh P. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010, C324S755090

Reexamination Certificate

active

06229324

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to testing of semiconductor components, such as chip scale packages and are dice. More particularly, this invention relates to a test system with mechanical alignment and to a method for fabricating the test system.
BACKGROUND OF THE INVENTION
A recently developed semiconductor package is known as a “chip scale package” or a “chip size package”. The dice contained in these packages are referred to as being “minimally packaged”. Chip scale packages can be constructed in “cased” or “uncased” configurations. Cased chip scale packages have a peripheral outline that is slightly larger that an unpackaged die. Uncased chip scale packages have a peripheral outline that is about the same as an unpackaged die.
Typically, a cased chip scale package includes a substrate formed of plastic, ceramic, or other electrically insulating material bonded to the face of the die. The substrate can include external contacts for making outside electrical connections to the chip scale package. For example, the external contacts for a chip scale package can comprise contact bumps arranged in a ball grid array (BGA), or a fine ball grid array (FBGA). Typically, the external contacts comprise a solder material, that permits the chip scale package to be flip chip bonded to a printed circuit board, or other substrate. Uncased chip scale packages can include external contacts formed directly on the device bond pads in the manner of a bumped die.
Following the manufacturing process, chip scale packages must be tested and burned-in. Test apparatus can be used to house one or more chip scale packages for testing, and to make temporary electrical connections with the external contacts on the chip scale packages. The test apparatus can include an interconnect component having contact members adapted to make the temporary electrical connections with the external contacts on the chip scale packages.
For making the electrical connections the contact members on the interconnect must be aligned with the external contacts on the chip scale packages. One method of alignment is with an optical alignment system such as described in U.S. Pat. No. 5,634,267 to Wood et al. Another method of alignment is with a mechanical alignment system.
The present invention is directed to a test system with an improved mechanical alignment system. The test system can be used to test chip scale packages or other semiconductor components such as bare semiconductor dice.
SUMMARY OF THE INVENTION
In accordance with the present invention, a test system for semiconductor components, and a method for fabricating the test system are provided. The components can be chip scale packages, or bare semiconductor dice, having external contacts in the form of contact bumps.
The test system includes a base for retaining one or more components, and multiple interconnects having contact members for making temporary electrical connections with the external contacts on the components. The test system also includes a mechanical alignment fixture having alignment surfaces for aligning the components to the interconnects. A single alignment fixture can be formed on the base, or separate alignment fixtures can be formed on each interconnect. In addition to the alignment fixture, the components can include alignment members configured to interact with the alignment surfaces on the alignment fixture and guide the components into alignment with the interconnects. Illustrative alignment members include beveled edges, alignment bumps, and alignment posts formed on the components.
Several different embodiments of alignment fixtures are disclosed. In each embodiment the alignment fixtures include alignment surfaces of a desired configuration. For example, the alignment surfaces can include openings in the alignment fixtures sized to engage the alignment members on the components. The alignment surfaces can also be configured for engaging the edges of the components, or for engaging the contact bumps on the components. Still further, the alignment surfaces can be configured for a two stage alignment procedure including a coarse alignment stage and a fine alignment stage. In the two stage embodiment, a first layer of the alignment fixture can provide a first surface for coarse alignment, while a second layer of the alignment fixture can provide a second surface for fine alignment.
The alignment fixture can comprise a polymeric material, such as a thick film resist, which is deposited on the interconnects, developed with alignment surfaces, and then cured. Preferably, the thick film resist is deposited on a wafer that includes multiple interconnects, which are singulated following development and curing of the resist. Alternately, the alignment fixture can comprise a polymer tape applied to the interconnects in a desired pattern. As another alternative, the alignment fixture can comprise a separate plate attached to the interconnects, or to the base of the system.


REFERENCES:
patent: 5006792 (1991-04-01), Malhi et al.
patent: 5046239 (1991-09-01), Miller et al.
patent: 5088190 (1992-02-01), Malhi et al.
patent: 5172050 (1992-12-01), Swapp
patent: 5196726 (1993-03-01), Nishiguichi et al.
patent: 5329423 (1994-07-01), Scholz
patent: 5341564 (1994-08-01), Akhavain et al.
patent: 5483174 (1996-01-01), Hembree et al.
patent: 5495179 (1996-02-01), Wood et al.
patent: 5500605 (1996-03-01), Chang
patent: 5519332 (1996-05-01), Wood et al.
patent: 5530376 (1996-06-01), Lim et al.
patent: 5541525 (1996-07-01), Wood et al.
patent: 5543725 (1996-08-01), Lim et al.
patent: 5559444 (1996-09-01), Farnworth et al.
patent: 5572140 (1996-11-01), Lim et al.
patent: 5574383 (1996-11-01), Saito et al.
patent: 5578934 (1996-11-01), Wood et al.
patent: 5592736 (1997-01-01), Akram et al.
patent: 5625298 (1997-04-01), Hirano et al.
patent: 5633122 (1997-05-01), Tuttle
patent: 5634267 (1997-06-01), Farnworth et al.
patent: 5691649 (1997-11-01), Farnworth et al.
patent: 5703493 (1997-12-01), Weeks et al.
patent: 5756370 (1998-05-01), Farnworth et al.
patent: 5834945 (1998-11-01), Akram et al.
patent: 5915977 (1999-06-01), Hembree et al.
patent: 5931685 (1999-08-01), Hembree et al.
patent: 5962921 (1999-10-01), Farnworth et al.
patent: 6005288 (1999-12-01), Farnworth et al.
patent: 6016060 (2000-01-01), Akram et al.
patent: 6018249 (2000-01-01), Akram et al.
patent: 6040702 (2000-03-01), Hembree et al.
patent: 6072326 (2000-06-01), Akram et al.
patent: 6077723 (2000-06-01), Farnworth et al.
patent: 6091252 (2000-07-01), Akram et al.
Lorenz, H. et al., “Suss report”, brochure, vol. 10, Third/Fourth Quarter, 1996.

Affiliated with

Also associated with

Rating

Test system with mechanical alignment for semiconductor chip... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test system with mechanical alignment for semiconductor chip..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test system with mechanical alignment for semiconductor chip... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2459243