Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1998-10-22
2001-07-31
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S510000, C438S422000
Reexamination Certificate
active
06268637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to an isolation structure and to a method of making the same incorporating an air gap.
2. Description of the Related Art
The implementation of integrated circuits involves connecting isolated circuit devices through specific electrical pathways. Where integrated circuits are implemented in silicon, it is necessary, therefore, to initially isolate the various circuit devices built into the silicon substrate from one another. The circuit devices are thereafter interconnected to create specific circuit configurations through the use of global interconnect or metallization layers and local interconnect layers.
Local oxidation of silicon (“LOCOS”) and trench and refill isolation represent two heavily used isolation techniques for both bipolar and metal oxide semiconductor (“MOS”) circuits. In a conventional semi-recessed LOCOS process, a thin pad oxide layer is thermally grown on a silicon substrate surface and coated with a layer of chemical vapor deposition (“CVD”) silicon nitride. The active regions of the substrate are then defined with a photolithographic step. The nitride layer is then dry etched and the pad oxide layer wet or dry etched with the photoresist left in place to serve as a masking layer for a subsequent channel stop implant. After the channel stop implant, field oxide regions are thermally grown by means of a wet oxidation step. The oxidation of the silicon proceeds both vertically into the substrate and laterally under the edges of the nitride layer, resulting in the formation of structures commonly known as bird's beaks.
The formation of bird's beak structures is problematic in a number of ways. To begin with, bird's beak formation can create significant limitations on the packing density of devices in an integrated circuit. Design rules for LOCOS processes must restrict the gaps between adjacent devices to account for the lateral encroachment of bird's beaks. In addition, the very shape of a bird's beak can result in the exposure of the substrate surface during subsequent overetching to open contacts for metallization. This can result in the source of the transistor becoming shorted to the well region when the metal interconnect film is deposited. This problem may be particularly acute in CMOS circuits where shallower junctions are used, due to the higher propensity for the exposure of the well regions. While some improvement in the formation of bird's beak structures has occurred as a result of the introduction of techniques such as the etchback of portions of the field oxide structures, deposition of a silicon nitride layer without a pad oxide layer, and use of a thin pad oxide covered with polysilicon, the difficulties associated with bird's beak formation have not been completely eliminated.
In trench based isolation structures, a damascene process is used to pattern and etch a plurality of trenches in the silicon substrate. The trenches are then refilled with a CVD silicon dioxide or doped glass layer that is planarized back to the substrate surface using etchback planarization or chemical mechanical polishing (“CMP”). Although conventional trench and refill isolation techniques eliminate the difficulties associated with bird's beak formation in LOCOS processes, there are nevertheless difficulties associated with the trench and refill isolation techniques. Some of these difficulties include the inversion of the silicon at the sidewalls of p-type active regions which can lead to latch-up conditions in CMOS circuits, and the development of sidewall and edge-parasitic conduction stemming from a lack of planarity between the trench isolation material and the active areas.
The problem of sidewall inversion is caused by the horizontal parasitic MOS device, with the well acting as the gate electrode and the trench dielectric acting as the MOS gate oxide. The voltage across this parasitic device will normally be the nominal operating voltage of the device, e.g., 3.3 or 5 volts. This gate voltage and the narrow trench width can cause inversion along the sidewall, outside of, but facing the well. At the onset of sidewall inversion, n-channel devices with source/drain regions butted to the same sidewall can become electrically connected by a path along the sidewall.
Another other potential drawback of trench and reflow isolation processing is the requirement for a very high degree of planarization of the trench dielectric and the substrate surface. To ensure that the CVD silicon dioxide trench isolation material is removed from all of the active areas at the conclusion of a typical etchback step, an overetch of the trench isolation material of at least 200 to 500 Å is performed. The trench isolation material is thus etched below the active area surface, exposing a portion of the active area sidewall. This exposed sidewall can lead to sidewall and edge parasitic conduction which can result in significant leakage currents and correspondingly poor device performance. CMP planarization can typically yield more highly planarized trench isolation dielectric and substrate surfaces. However, there remains the potential for small differentials in the upper surfaces of the substrate and the trench isolation dielectric at the interface between the two structures due primarily to differential polish rates during the CMP process.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, an isolation structure positioned in a trench in a substrate is provided. The isolation structure includes a first insulating sidewall and a second insulating sidewall positioned in spaced-apart relation to the first insulating sidewall. A bridge layer is coupled to the first and second insulating sidewalls. The bridge layer, the first and second insulating layers and the substrate define an air gap in the trench.
In accordance with another aspect of the present invention, an integrated circuit is provided that includes a substrate that has a trench. A first circuit device is positioned on the substrate and a second circuit device is positioned on the substrate. An isolation structure is positioned in the trench and separates the first and second circuit devices. The isolation structure has a first insulating sidewall, a second insulating sidewall positioned in spaced-apart relation to the first insulating sidewall, and a bridge layer coupled to the first and second insulating sidewalls. The bridge layer, the first and second insulating layers and the substrate define an air gap in the trench.
In accordance with another aspect of the present invention, a method of fabricating an electrical isolation structure in a substrate is provided that includes the steps of forming a trench in the substrate and forming a first insulating sidewall in the trench and a second insulating in the trench in spaced-apart relation to the first insulating sidewall. A bridge layer is formed between the first and the second sidewalls. The bridge layer, the first and second sidewalls, and substrate define an air gap in the trench.
REFERENCES:
patent: 4106050 (1978-08-01), Riseman
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patent: 5926721 (1999-07-01), Hong et al.
Stanley Wolf and Richard N. Tauber;Silicon Processing for the VLSI Era, Volume 1—Process Technology; pp. 124-135; 1986.
Gardner Mark I.
Hause Frederick N.
May Charles E.
Advanced Micro Devices , Inc.
Honeycutt Timothy M.
Prenty Mark V.
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