Semiconductor device which reduces the minimum distance...

Details Semiconductor device which reduces the minimum distance... Semiconductor device which reduces the minimum distance...

1996-07-24

2001-08-28

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S304000, C257S774000, C438S359000, C438S424000

Reexamination Certificate

active

06281562

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including transistors and connection between the transistors for constituting an LSI with high integration and a decreased area.
With the recent development of a semiconductor device with high integration and high performance, there are increasing demands for more refinement of the semiconductor device. The improvement of the conventional techniques cannot follow these demands, and novel techniques are unavoidably introduced in some technical fields. For example, as a method of forming an isolation, the LOCOS isolation method is conventionally adopted in view of its simpleness and low cost. Recently, however, it is considered that a trench buried type isolation (hereinafter referred to as the trench isolation) is more advantageous for manufacturing a refined semiconductor device.
Specifically, in the LOCOS isolation method, since selective oxidation is conducted, the so-called bird's beak occurs in the boundary with a mask for preventing the oxidation. As a result, the dimension of a transistor is changed because an insulating film of the isolation invades a transistor region against the actually designed mask dimension. This dimensional change is unallowable in the refinement of a semiconductor device after the 0.5 &mgr;m generation. Therefore, even in the mass-production techniques, the isolation forming method has started to be changed to the trench isolation method in which the dimensional change is very small. For example, IBM corporation has introduced the trench isolation structure as a 0.5 &mgr;m CMOS process for the mass-production of an MPU (IBM Journal of Research and Development, VOL. 39, No. 1/2, 1995, pp. 33-42).
Furthermore, in a semiconductor device mounting elements such as a MOSFET in an active area surrounded with an isolation, an insulating film is deposited on the active area, the isolation and a gate electrode, and a contact hole is formed by partly exposing the insulating film for connection between the active area and an interconnection member on a layer above the insulating film. This structure is known as a very common structure for the semiconductor device.
FIG. 17
is a sectional view for showing the structure of a conventional semiconductor device. In
FIG. 17
, a reference numeral
1
denotes a silicon substrate, a reference numeral
2
b
denotes an isolation with a trench isolation structure which is made of a silicon oxide film and whose top surface is flattened so as to be at the same level as the top surface of the silicon substrate
1
, a reference numeral
3
denotes a gate oxide film made of a silicon oxide film, a reference numeral
4
a
a denotes a polysilicon electrode working as a gate electrode, a reference numeral
4
b
denotes a polysilicon interconnection formed simultaneously with the polysilicon electrode
4
a
, a reference numeral
6
denotes a low-concentration source/drain region formed by doping the silicon substrate with an n-type impurity at a low concentration, a reference numeral
7
a
denotes an electrode sidewall, a reference numeral
7
b
denotes an interconnection sidewall, a reference numeral
8
denotes a high-concentration source/drain region formed by doping the silicon substrate with an n-type impurity at a high concentration, a reference numeral
12
denotes an insulating film made of a silicon oxide film, and a reference numeral
13
denotes a local interconnection made of a polysilicon film formed on the insulating film
12
.
The local interconnection
13
is also filled within a connection hole
14
formed in a part of the insulating film
12
, so as to be contacted with the source/drain region in the active area through the connection hole
14
. In this case, the connection hole
14
is formed apart from the isolation
2
b
by a predetermined distance. In other words, in the conventional layout rule for such a semiconductor device, there is a rule that the edge of a connection hole is previously located away from the boundary between the active area and the isolation region so as to prevent a part of the connection hole
14
from stretching over the isolation
2
b
even when a mask alignment shift is caused in photolithography (this distance between the connection hole and the isolation is designated as an alignment margin).
However, in the structure of the semiconductor device as shown in
FIG. 17
, there arise problems in the attempts to further improve the integration for the following reason:
A distance La between the polysilicon electrode
4
a
and the isolation
2
b
is estimated as an index of the integration. In order to prevent the connection hole
14
from interfering the isolation
2
b
as described above, the distance La is required to be 1.2 &mgr;m, namely, the sum of the diameter of the connection hole
14
, that is, 0.5 &mgr;m, the width of the electrode sidewall
7
a,
that is, 0.1 &mgr;m, the alignment margin from the polysilicon electrode
4
a
, that is, 0.3 &mgr;m, and the alignment margin from the isolation
2
b
, that is, 0.3 &mgr;m. A connection hole has attained a more and more refined diameter with the development of processing techniques, and also a gate length has been decreased as small as 0.3 &mgr;m or less. Still, the alignment margin in consideration of the mask alignment shift in the photolithography is required to be approximately 0.3 &mgr;m. Accordingly, as the gate length and the connection hole diameter are more refined, the proportion of the alignment margin is increased. This alignment margin has become an obstacle to the high integration.
Therefore, attempts have been made to form the connection hole
14
without considering the alignment margin in view of the alignment shift in the photolithography. Manufacturing procedures adopted in such a case will now be described by exemplifying an n-channel MOSFET referring to FIGS.
18
(
a
) through
18
(
c
).
First, as is shown in FIG.
18
(
a
), after forming an isolation
2
b
having the trench structure in a silicon substrate
1
doped with a p-type impurity (or p-type well), etch back or the like is conducted for flattening so as to place the surfaces of the isolation
2
b
and the silicon substrate
1
at the same level. In an active area surrounded with the isolation
2
b
, a gate oxide film
3
, a polysilicon electrode
4
a
serving as a gate electrode, an electrode sidewall
7
a
, a low-concentration source/drain region
6
and a high-concentration source/drain region
8
are formed. On the isolation
2
b
are disposed a polysilicon interconnection
4
b
formed simultaneously with the polysilicon electrode
4
a
and an interconnection sidewall
7
b
. At this point, the top surface of the high-concentration source/drain region
8
in the active area is placed at the same level as the top surface of the isolation
2
b
. Then, an insulating film
12
of a silicon oxide film is formed on the entire top surface of the substrate.
Next, as is shown in FIG.
18
(
b
), a resist film
25
a
used as a mask for forming a connection hole is formed on the insulating film
12
, and the connection hole
14
is formed by, for example, dry etching.
Then, as is shown in FIG.
18
(
c
), the resist film
25
a
is removed, and a polysilicon film is deposited on the insulating film
12
and within the connection hole
14
. The polysilicon film is then made into a desired pattern, thereby forming a local interconnection
13
.
At this point, in the case where the alignment margin in view of the mask alignment shift in the formation of the connection hole
14
is not considered in estimating the distance La between the polysilicon electrode
4
a
and the isolation
2
b
, a part of the isolation
2
b
is included in the connection hole
14
when the exposing area of the resist film
25
a
is shifted toward the isolation
2
b
due to the mask alignment shift in the photolithography. Through over-etch in conducting the dry etching of the insulating film
12
, although the high-concentration source/drain region
8
made of the silicon substrate is not largely etc

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