Phase locked loop wherein phase comparing and filtering are perf

Details Phase locked loop wherein phase comparing and filtering are perf Phase locked loop wherein phase comparing and filtering are perf

1988-09-21

1989-09-05

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 2, 331 17, 331 25, H03L 718, H03L 722

Patent

active

048642533

ABSTRACT:
A phase-locked loop is formed by a series circuit of a counter, a register, an arithmetic unit, a low-pass filter, a PI-filter, and a voltage-controlled oscillator. The digital, internal clock signals generated by the oscillator are counted in a counter and are transferred into the register and stored as a current counter reading at points in time determined by time interval clock signals. For example, the time interval clock signals are acquired from reference clock signals by means of a divider and exhibit a lower frequency than the internal clock signals. A drive signal in digital form is determined in the arithmetic unit on the basis of the current counter reading, on the counter reading of the preceding evaluation interval, and on a rated value. This drive signal proceeds via a digital low-pass filter, PI-filter, and D/A converter to the control input of the oscillator, and controls the latter such that the internal clock signals coincide in phase with the reference clock signals.

REFERENCES:
patent: 4418318 (1983-11-01), Swagerty et al.
patent: 4450518 (1984-05-01), Klee
"A Microprocessor-Controlled Phase-Locked Loop for Network Synchronization", by Masatoshi Makino et al, Proceedings of 1979 ISCAS, pp. 804-805.

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