Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
1999-05-06
2001-07-10
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S118000, C341S143000
Reexamination Certificate
active
06259389
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the testing and design of integrator based analog-to-digital converter circuits, and more particularly to a method of designing and testing a sigma-delta based analog-to-digital converter circuit using optimized polynomial representations of the non-linearity of the transfer function of the circuit to predict the signal-to-noise ratio (SNR) and the signal-to-distortion ratio (SDR).
The timely design of integrated circuits for economical and reliable insertion into products and systems requires design methodologies which increase the likelihood of obtaining the required performance with little or no design iteration. Operation is required at the designed level of performance over manufacturing tolerances, and over expected environmental and operational conditions. Computer aided design (CAD) methods are used extensively in integrated circuit (IC) design to increase the robustness to variations in manufacturing tolerances as well as environmental and operational conditions. Enhanced CAD tools that enable rapid and verifiable product designs are a critical need to maintain the pace of productivity enhancement in IC development.
Semiconductor manufacturing processes have inherent limitations in the tolerances that can be maintained on key parameters important for analog and digital integrated circuit design. Limitations in lithography cause uncertainty in device geometry such as metal-oxide semiconductor (MOS) transistor length and width which determine amplifier gain-bandwidth and logic drive strength. Variability in oxide growth rate contributes to variable oxide thickness which in turn causes variability in transistor capacitance and transconductance. Uncertainties in doping profiles on implants and diffusions cause variance in resistor values as well as transistor parasitic capacitance. The circuit impact of these manufacturing tolerances must be considered when designing integrated circuits.
Once in a product or system, an integrated circuit must maintain the required level of performance over all expected conditions including temperature excursions, variations in power supply voltage, and fluctuations in input signal integrity. Since test of each chip produced over all expected environmental or operational condition is impractical, consideration of variations is critical in design of robust, reliable integrated circuits. To design an integrated circuit for robustness with respect to the always present variations, requires simulation of the circuit over the ranges of these variations. This task is reasonable for circuits such as op-amps, comparators, switches, and logic gates whose performance can be evaluated in direct time-domain simulations taking seconds, minutes, or hours. When the simulations require days or more to run on the fastest engineering workstations, the design cycle becomes too long to practically meet the market demands for the technology. In situations where direct circuit simulations are impractical, other CAD methods must be employed.
Design of complex, mixed analog-digital integrated circuits poses challenges to designers, and places strong demands on CAD tools. Circuits such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and phase-lock loops (PLLs) are examples of circuits which challenge direct time-domain simulation. The common feature of these circuits is that the circuits resist linearization since they operate in several different linear and non-linear regimes. The result is complex transient behavior which requires time-domain simulation with a fine time-step.
With the advent of the introduction of computers into most products and systems, the need for circuits to interface between our analog world and the digital world of the computer has increased dramatically. The growing need for high performance, low power, and low cost electronic systems has resulted in the invention of many elegant ADC circuits. As the resolution increases, more power is required to increase the sample rate. The decreasing efficiency with resolution is related to difficulties associated with component matching and absolute voltage and current accuracy required, which are limited by semiconductor process technology and power supply levels. When resolutions increase, circuit complexity increases to compensate for the limitations in component matching and accuracy limits. The circuit complexity increases the power consumption accordingly.
The low resolution ADCs are typically pipelined or folded flash architectures. The high resolution converters are typically dual-slope, successive approximation, or sigma-delta architectures. The sigma-delta architecture is capable of attaining high resolution analog-to-digital conversion with moderate sample rates and low power consumption in a CMOS process, and this makes it attractive for integration into mixed analog-digital circuits. The sigma-delta modulator uses oversampling of the input signal combined with low resolution quantization and digital filtering to accomplish analog-to-digital conversion. The oversampling of the low bandwidth signal poses a particularly difficult problem in circuit simulation of sigma-deltas. High accuracy analog simulations need to be run for many sample periods to evaluate the result of conversion after digital filtering. Simulations in a circuit simulator, such as SPICE™, may take days for a single case, with the simulated performance perhaps limited to less than 15 bits due to rounding and truncation errors which accumulate over the large number, possibly millions, of time steps required for accurate simulation.
Several CAD methods for the simulation of sigma-delta modulators have been developed. The existing methods are useful in determining the performance of subcircuits required to achieve a desired level of performance, or to verify the performance once all the subcircuits have been designed. However, a methodology which is useful in optimizing the subcircuit designs is clearly lacking. A methodology which can quickly and easily estimate the sigma-delta performance given simulation data of the subcircuits could be used in the automated optimization of the subcircuits and lead to shorter design cycles and more robust designs. As such, a sigma-delta method is desired which does not rely on simulation of the sigma-delta loop in order to evaluate the SNR and SDR of a modulator instance.
Simulation and testing of over-sampled analog-to-digital converters (ADCs) requires the simulation or acquisition of thousands of consecutive samples in order to determine resolution and linearity. Typically the ADC is run for 16K to 64K clock cycles and an Fast Fourier Transform (FFT) performed on pre-decimated or post-decimated samples. The signal-to-noise ratio (SNR) and signal-to-distortion ratio (SDR) are computed from the FFT spectrum. The long time-domain modulator simulations consume significant design time. Testing a multi-channel ADC over several operational conditions using this method adds substantial cost to the integrated circuit. As such, it is desirable to reduce the test time so as to improve design optimization.
BRIEF DESCRIPTION OF THE INVENTION
The present invention provides a method and apparatus which uses data containing non-linearity information regarding integrator circuits in over-sampled Analog-to-Digital Converters (ADCs) to predict the Signal-to-Distortion Ratio (SDR) and Signal-to-Noise Ratio (SNR). The present invention determines the non-linearity and non-ideology of an analog-to-digital device under test, the device under test having at least one integrator, a respective non-linear integrator model, and non-linearity parameters. The present invention includes the following steps: generating a model data set from a plurality of simulations of the analog-to-digital device under test employing the respective non-linear integrator model; generating an n-dimensional prediction equation corresponding to the model data set; measuring the input response of each respective non-linear integrator to generate a respe
Breedlove Jill M.
General Electric Company
Thompson John F.
Wamsley Patrick
LandOfFree
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