Semiconductor device and method of manufacturing thereof

Details Semiconductor device and method of manufacturing thereof Semiconductor device and method of manufacturing thereof

1998-09-11

2001-06-05

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C257S756000, C257S757000

Reexamination Certificate

active

06242806

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. The invention more particularly relates to a semiconductor device and a method of manufacturing the same having a local interconnection line which connects impurity regions of different conductivity types.
2. Description of the Background Art
A static random access memory (hereinafter simply referred to as “SRAM”) is known as one example of a semiconductor device having impurity regions of different conductivity types connected by a local interconnection line.
FIG. 69
shows an equivalent circuit diagram of a conventional SRAM of CMOS (Complementary Metal Oxide Semiconductor) type disclosed in Japanese Patent Laying-Open No.2-150062, for example.
As shown in
FIG. 69
, a memory cell of the SRAM includes two pMOS transistors T
1
and T
3
for loads, and four nMOS transistors T
2
, T
4
, T
5
and T
6
.
The drain of one of a pair of driver nMOS transistors T
2
and T
4
is connected to the gate electrode of the other transistor, and the drains of PMOS transistors T
1
and T
3
for loads are respectively connected to the drains of transistors T
2
and T
4
. The sources of driver nMOS transistors T
2
and T
4
are fixed at a prescribed potential (e.g. ground potential), and supply voltage Vcc is applied to the sources of pMOS transistors T
1
and T
3
for loads. As a result, current is supplied to a flip-flop circuit constituted of driver nMOS transistors T
2
and T
4
and pMOS transistors for loads T
1
and T
3
.
Access nMOS transistors T
5
and T
6
are connected to storage nodes
17
a
and
17
b
of the flip-flop circuit described above. The gate electrodes of access nMOS transistors T
5
and T
6
are connected to a word line
6
.
The configuration of the memory cell of the CMOS type SRAM is described in detail using FIG.
70
.
FIG. 70
is a plan view of a memory cell corresponding to one bit of the CMOS type SRAM.
As shown in
FIG. 70
, an isolation oxide film
2
is formed in an element isolation region at a major surface of a semiconductor substrate. n
+
impurity regions
11
a
1
,
11
a
2
,
11
a
3
,
11
b
1
,
11
b
2
, and
11
b
3
are formed in an element formation region surrounded by isolation oxide film
2
. p
+
impurity regions
10
a
1
,
10
a
2
,
10
b
1
, and
10
b
2
are also formed in the element formation region. The n
+
impurity regions
11
a
1
-
11
b
3
form source/drain regions of driver nMOS transistors T
2
and T
4
and access nMOS transistors T
5
and T
6
. p
+
impurity regions
10
a
1
-
10
b
2
form source/drain regions of load PMOS transistors T
1
and T
3
.
A gate electrode
8
formed of polycrystal silicon, for example, functions as gate electrodes of load PMOS transistor T
3
and driver nMOS transistor T
4
. Gate electrode
8
has an extended portion located in the vicinity of load pMOS transistor T
1
. A gate electrode
7
functions as gate electrodes of load pMOS transistor T
1
and driver nMOS transistor T
2
, and has an extended portion located in the vicinity of driver nMOS transistor T
4
. A gate electrode
6
is used as gate electrodes of access nMOS transistors T
5
and T
6
and as a word line.
An insulating film (not shown) is formed to cover gate electrodes
6
-
8
. Interconnection lines
39
a
and
39
b
formed of an aluminum film is formed on the insulating film. p
+
impurity region
10
a
2
, the extended portion of gate electrode
7
and n
+
impurity region
11
a
2
are connected to each other by interconnection line
39
a
via contact holes
17
a,
16
a
and
15
a
formed at the insulating film. p
+
impurity region
10
b
2
, the extended portion of gate electrode
8
and n
+
impurity region
11
b
2
are connected to each other by interconnection line
39
b
via contact holes
15
b,
16
b
and
17
b
formed at the insulating film.
A cross sectional structure along the X
1
-X
2
line of
FIG. 70
is described using FIG.
71
.
Referring to
FIG. 71
, a p well
3
and an n well
4
are formed at the major surface of semiconductor substrate
1
. n
+
impurity regions
11
a
2
and
11
a
3
are formed in p well
3
, and p
+
impurity region
10
a
2
is formed in n well
4
.
Sidewall insulating films
9
are formed on sidewalls of gate electrodes
6
-
8
. An interlayer insulating film
12
is formed to cover gate electrodes
6
-
8
. At interlayer insulating film
12
, contact hole
15
a
reaching impurity region
11
a
2
, contact hole
16
a
reaching gate electrode
7
and contact hole
17
a
reaching p
+
impurity region
10
a
2
are formed.
Local interconnection line
39
a
formed of an aluminum film is formed to extend from the inside of contact holes
15
a
-
17
a
onto interlayer insulating film
12
. An interlayer insulating film
20
is formed to cover interconnection line
39
a
. A contact hole
21
is formed to reach n
+
impurity region
11
a
3
through interlayer insulating film
20
and interlayer insulating film
12
. An aluminum interconnection line
22
is formed to extend from the inside of contact hole
21
onto interlayer insulating film
20
.
As described above, local interconnection line
39
a
connecting p
+
impurity region
10
a
2
and n
+
impurity region
11
a
2
is constituted of a metallic film such as an aluminum film in order to prevent a pn junction from being formed in an interconnection line when impurity regions of different conductivity types are connected.
However, a problem described below arises when a metallic film such as an aluminum film is used as local interconnection line
39
a.
Local interconnection
39
a
is in contact with n impurity region
11
a
2
via a contact portion
40
, in contact with gate electrode
7
via a contact portion
41
, and in contact with p
+
impurity region
10
a
2
via a contact portion
42
. Accordingly, impurities in n
+
impurity region
11
a
3
, in p
+
impurity region
10
a
2
, and in gate electrode
7
are sucked up by local interconnection line
39
a
. A problem in this case is, that contact resistance increases at contact portions
40
-
42
.
Further, there is another problem of generation of leakage current caused by diffusion of a metallic component in local interconnection line
39
a
into semiconductor substrate
1
at contact portions
40
and
42
.
Consequently, a problem of degradation of reliability of the SRAM is caused. The problems described above are not for the SRAM only, but for a semiconductor device having an interconnection line which connects an n type impurity region and a p type impurity region.
SUMMARY OF THE INVENTION
The present invention is made to solve the problems as described above. An object of the invention is, for a semiconductor device having an interconnection line which connects impurity regions of different conductivity types, to reduce contact resistance between the interconnection line and impurity regions, and to restrict generation of leakage current.
A semiconductor device according to one aspect of the present invention includes first and second impurity regions, an insulating layer and an interconnection layer. The first impurity region of a first conductivity type is formed at a surface of a semiconductor substrate. The second impurity region of a second conductivity type is formed at the surface spaced from the first impurity region. The insulating layer is formed on the surface of the semiconductor substrate and has first and second contact holes that reach the first and second impurity regions. The interconnection layer includes a nonmetallic conductive film electrically connecting the first and second impurity regions via the contact holes, covering inner bottom portions of the contact holes and side portions thereof, and in contact with respective first and second impurity regions, and includes a metallic conductive film connected to the nonmetallic conductive film without being in contact with a surface of the nonmetallic conductive film located at the inner bottom porti

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