Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-05-03
2001-01-09
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030
Reexamination Certificate
active
06172912
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a multilevel programming method for a semiconductor storage, in particular, for floating gate type nonvolatile semiconductor storage of a virtual ground memory array.
(2) Description of the Related Art
In recent years, virtual ground type flash memory devices aiming for high packing density have drawn attention, such as for example, ‘A New Cell Structure for Sub-quarter Micron High Density Flash Memory’ (IEDM Technical Digest, pp.269-270, 1995), and an ACT (Asymmetrical Contactless Transistor) type flash memory disclosed in ‘An investigation of a sensing method of an ACT type flash memory’ (ICD97-21, p.37, 1997, a technical report of The Institute of Electronics, Information and Communication Engineers).
In such an ACT type flash memory, programming and erasing operations are implemented based on the FN (Fowler-Nordheim) tunnel effect, and it is expected to be used for data storage type.
Referring now to
FIGS. 1 and 2
, the ACT type flash memory will be described.
An ACT type flash memory uses the FN tunnel effect when programming and erasing as stated above, and has a virtual ground array configuration in which each bit line is shared between two memory cells. In this way, in an ACT type flash memory, the bit lines are shared and formed of a diffusion layer to thereby reduce the number of contacts and enable a remarkable reduction of the array area, which leads to high integration.
Next, an ACT type flash memory device, as sectionally shown in
FIGS. 2A and 2B
, has, in order from the top, a control gate WL, an inter-layer insulating layer, a floating gate FG and a bit line (diffusion layer) arranged in a layered manner. The common bit line formed under and between the adjacent floating gates FG has different donor densities between the drain and source sides.
In
FIG. 1
where ACT type flash memory cells are arranged in an arrayed configuration, MBLx represents main bit lines, SBLx represents sub-bit lines formed of a diffusion layer, WLx represents word lines, SGx represents gate selection signal lines, CONTACT represents a contact point between a main bit line and a sub-bit line (belonging to different layers).
Next, programming and erasing operations for an ACT type flash memory using the FN tunnel effect will be described.
First, programming the ACT type flash memory (see
FIG. 2A
) is performed with a negative voltage of −8 volts (‘volts’ will be abbreviated hereinbelow as ‘V’) applied to gate WL and a positive voltage of 5 V applied to the drain side. By this voltage application, the FN tunnel effect occurs on the drain side so that electrons are extracted from floating gate FG to the drain side. This extraction of electrons lowers the threshold level, which means that programming is implemented.
An erase operation is performed with a high voltage (+10 V) applied to gate WL and a negative voltage (−8 V) applied to the bit lines and the substrate (P-portion) so as to generate the FN tunnel effect between the channel layer and floating gate FG to thereby inject electrons into the floating gate FG. This injection of electrons raises the threshold level, which means that erasing is implemented.
The operating principle of one ACT type flash memory (memory cell) M schematically shown in
FIG. 3
will be described more detailedly.
In an ACT type flash memory M, a control gate
100
, a inter-layer insulating layer
101
, a floating gate
102
and a tunnel oxide film
103
are formed in layers and this layered structure is placed over and between a drain
105
and source
106
formed within a substrate
104
. As already mentioned, drain
105
and source
106
have different donor densities from each other.
In the beginning, for a program operation, or to extract electrons from floating gate
102
, a negative voltage Vnw (−8 V) is applied to control gate
100
, a positive voltage Vpp (+5 V) is applied to drain
105
and source
106
is set floating. Under these conditions, electrons are drawn from floating gate
102
by the FN tunnel effect, and thereby the threshold level of memory cell M is lowered to about 1.5 V.
For an erase operation, or to inject electrons into floating gate
102
, a positive voltage Vpe (+10 V) is applied to control gate
100
, a negative voltage Vns (−8 V) is applied to source
106
and drain
105
is set floating. Under the conditions electrons are injected into floating gate
102
by the FN tunnel effect and thereby the threshold level of memory cell M is raised over about 4 V.
A flash memory as above which uses the FN tunnel effect for both program and erase operations is called an FN—FN operating flash memory.
For a read operation, 3 V is applied to control gate
100
, 1 V is applied to drain
105
, 0 V is applied to source
106
. The current flowing through cell M under the conditions, is detected by an unillustrated sensing circuit to read out the data.
The application of voltage for the above operations is summarized in Table 1.
TABLE 1
Application of voltage to a conventional flash memory
Control Gate
Drain
Source
P-type Well
Program
−8 V
5 V
Open
0 V
Erase
10 V
Open
−8 V
−8 V
Read
3 V
1 V
0 V
0 V
In the field of memory technology, as an attempt to aim at higher integration, multilevel techniques for introducing three or more threshold levels to each memory cell have been published. Examples of the multilevel technology include the following methods.
A first conventional method (conventional method 1) is disclosed in 1997 ISSCC Dig. Tech. Papers, pp36-37 “A 98 mm
2
3.3V 64 Mb Flash Memory with FN-NOR Type-4level cell” and in Japanese Patent Application Laid-Open Hei 6 No.177,397.
A second conventional method (conventional method 2) is disclosed in 1997 ISSCC Dig. Tech. Papers, pp32-33 “A 3.3V 128 Mb Multilevel NAND Flash Memory For Mass Storage Applications” and in Japanese Patent Application Laid-Open Hei 9 No.7,383.
In the conventional method 1, an FN-NOR type flash memory is used. The flowchart of the algorithm for programming memory cell M is shown in FIG.
4
. In this case, for data ‘11’, ‘10’, ‘01’, programming pulses are simultaneously applied by applying different voltages to drains
105
, making use of the threshold level voltage-to-time characteristic shown in FIG.
5
. Based on this characteristic, each cell is programmed so as to have a voltage level falling within one of the threshold levels in the distribution shown in
FIG. 6
(Step S
20
).
As shown in
FIG. 6
, data ‘00’ is the erased state. Subsequently, a verify operation (data verification after programming) (Step S
21
) is performed in two stages.
At the first stage, the reference voltage (the standard voltage with which comparison is made) is set at around 2.3 V, for example, so as to judge whether the threshold level falls within the ‘11’ and ‘10’ states or within the ‘01’ and ‘00’ states (see FIG.
6
).
Next, at the second stage, a different operation will be effected based on the sensed result from the first stage. When the sensed result from the first stage falls within the ‘11’ and ‘10’ states, then the reference voltage is set at 1.3 V, for example, so as to determine whether the threshold level is ‘11’ or ‘10’. When the sensed result from the first stage falls within the ‘01’ and ‘00’ states, then the reference voltage is set at 3.3 V, for example, so as to determine whether the threshold level is ‘01’ or ‘00’.
The above operations, that is, application of the programming pulses and verification, are repeated based on the verification result until the desired threshold level is obtained (Steps
20
and
21
in FIG.
4
). Generally, the characteristics of the change in threshold level fluctuates when the FN tunnel effect is used, so that a pulse width shorter than that meeting the actual characteristic is used. That is, pulse applications (voltage application to the bit lines) are stopped in the order in which programming is completed, so as to set the designated threshold levels whilst preventing the
Hirano Yasuaki
Ohta Yoshiji
Morrison & Foerster / LLP
Nelms David
Sharp Kabushiki Kaisha
Yoha Connie C.
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