Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Utility Patent
1998-03-24
2001-01-02
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S439000
Utility Patent
active
06169011
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
This invention relates generally to integrated circuit (IC) fabrication processes, and more specifically to a trench isolation structure and method of forming an isolation trench which maintains a minimally thick gate oxide layer.
To prevent the flow of leakage currents between transistors in an IC, adjoining transistors must be isolated. As the size of the transistors decreases and the density of transistors in an IC increases, the isolation structures between transistors becomes more important. Growing oxide as an isolation structure through the localized oxidation of silicon (LOCOS) often results in the formation of a large “bird's beak”. A bird's beak is a tapered wedge of oxide over a silicon substrate active areas. The bird's beak interferes with subsequently formed gate oxide layers. Ultimately, the drain current of narrow channel width transistors is impacted.
A trench isolation method was developed in response to the bird's beak problem associated with the LOCOS isolation method. Typically, a gate oxide layer is formed over a silicon substrate, with a SiN layer overlying the gate oxide layer. A trench is etched through the SiN layer, the gate oxide layer, and into the silicon substrate. The trench is then filled with oxide. Unfortunately, the planarization of the surface, of excess oxide often leaves the top surface of the oxide-filled trench either slightly above, or slightly below the gate oxide layer. Typically, the gate oxide at the point of intersection is thin. These areas of thin gate oxide cause the subsequently formed transistor to have a low breakdown voltage and high leakage current.
It would be advantageous if transistors isolated by a trench isolation structure had a high breakdown voltage.
It would be advantageous if a minimum gate oxide layer thickness could be maintained when trench isolation is used to isolated adjacent transistors.
It would be advantageous if the minimum gate oxide thickness could be maintained in a relatively simple refinement to the standard trench isolation procedure.
Accordingly, in an integrated circuit, a method for isolating transistors on a silicon substrate with a trench structure has been provided. The method comprising the steps of:
a) forming a layer of gate insulator material selected from the group consisting of silicon oxide, TiO
2
, and Ta
3
O
5
, and having a first uniform thickness in the range between 2 and 10 nanometers (nm) overlying the silicon substrate;
b) forming a first layer of gate electrode material selected from the group consisting of polysilicon, W, and Mo, having a surface and a second thickness in the range between 20 and 100 nm, overlying the gate insulator layer;
c) etching a predetermined area of the silicon substrate, forming a silicon substrate trench with a third thickness in the range between 300 and 700 nm, through the overlying gate insulator and first gate electrode layers, forming a trench with first gate electrode sidewalls, which overlie gate insulator sidewalls, which overlie silicon substrate sidewalls;
d) oxidizing exposed surfaces to a fourth thickness in the range between 5 and 50 nm, including the silicon substrate and first gate electrode sidewalls of the trench;
e) filling the trench with oxide; and
f) planarizing to remove oxide and a portion of the first gate electrode material from the surface of the first gate electrode layer, forming a first gate electrode layer fifth thickness in the range between 20 and 100 nm. A minimally thick gate insulator is formed to prevent low breakdown voltages.
The method further comprising the steps, following Step f), of:
g) depositing a second layer of gate electrode material, of the same material as the first gate electrode layer, selected from the group consisting of polysilicon, W, and Mo, and having a sixth thickness in the range between 100 and 300 nm overlying the surface of the first gate electrode layer and the oxide-filled trench; and
h) selectively etching a predetermined area of the second gate electrode layer, and underlying first gate electrode layer to form a gate electrode overlying predetermined areas of the gate insulator layer and trench. A transistor gate electrode is formed with a large gate breakdown voltage and low leakage currents due to the gate insulator having a uniform thickness of at least 2 nm. By uniform thickness it is meant that the gate insulator thickness along the edge of the source and drain regions, adjoining the oxide trench, are at least as thick as any other region of gate insulator thickness, such as the region underlying the gate electrode. In some aspects of the invention, the gate insulator first thickness adjoining the isolation trench is even slightly larger than the thickness of insulator underlying the gate electrode.
An integrated trench structure and a process to form a trench structure to isolate transistors on a silicon substrate are also provided. The trench structure comprises a layer of gate insulator material having a first uniform thickness overlying the silicon substrate, and a layer of first gate electrode material having a surface and a fifth thickness overlying the gate oxide layer.
A trench is formed by etching from a predetermined area of said first gate electrode layer surface, through said gate insulator layer, and into the silicon substrate forming a silicon substrate trench having a third thickness, and forming first gate electrode layer trench sidewalls, overlying gate insulator layer trench sidewalls, overlying silicon substrate trench sidewalls.
Oxidized trench sidewalls having a fourth thickness are formed by oxidizing the first gate electrode layer sidewalls and the silicon substrate trench sidewalls. The oxidized sidewalls separate the first gate electrode material and the silicon substrate from the trench.
A trench oxide structure formed by filling the trench with oxide, planarizing a second thickness of the first gate electrode layer down to the fifth thickness, while planarizing the oxide-filled trench to the surface level of the first gate electrode layer fifth thickness. A uniformly thick oxide layer insulates the overlying first gate electrode layer from the silicon substrate.
The trench structure further comprises a completed gate electrode formed by depositing a layer of second gate electrode material having a sixth thickness overlying the surface of the first gate electrode layer and the oxide-filled trench. A predetermined area of the second gate electrode layer, and underlying first gate electrode layer are selectively etched to form the completed gate electrode overlying predetermined areas of the gate insulator layer and trench. The completed transistor gate electrode is formed with a large breakdown voltage and low leakage currents due to the uniform thickness of the gate insulator.
REFERENCES:
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patent: 5387540 (1995-02-01), Poon et al.
patent: 5436488 (1995-07-01), Poon et al.
patent: 5874325 (1999-02-01), Koike
patent: 5972778 (1999-10-01), Hamada
patent: 6002160 (1999-12-01), He et al.
K. Shibahara et al., “Trench Isolation with (Nabla)-shaped Buried oxide for 256 MEGA-BIT DRAMS” pp 10.5.1-10.5.4, IDEM 92-275 Dec. 1992.
Chaudhuri Olik
Coleman William David
Rabdau Matthew D.
Ripma David C.
Sharp Laboratories of America Inc.
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