Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
1998-12-30
2001-04-03
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C712S023000, C712S219000
Reexamination Certificate
active
06212626
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to a computer processor. More particularly, the present invention is directed to a checker that checks instructions within a computer processor.
BACKGROUND OF THE INVENTION
The primary function of most computer processors is to execute computer instructions. Most processors execute instructions in the programmed order that they are received. However, some recent processors, such as the Pentium® II processor from Intel Corp., are “out-of-order” processors.
An out-of-order processor can execute instructions in any order as the data and execution units required for each instruction becomes available. Some instructions in a computer system are dependent on one other through machine registers. Out-of-order processors attempt to exploit parallelism by actively looking for instructions whose input sources are available for computation, and scheduling them ahead of programmatically later instructions. This creates an opportunity for more efficient usage of machine resources and overall faster execution.
An out-of-order processor can also increase performance by reducing overall latency. This can be done by speculatively scheduling instructions while assuming that the memory subsystem used by the processor is perfect. Therefore, the processor may assume that all cache accesses are hits. This allows dependent arithmetic and logical instructions to be scheduled without the full latency of receiving a confirmation from the memory subsystem that they were executed correctly.
An out-of-order processor that speculatively schedules instructions requires a mechanism to re-execute incorrectly performed instructions. One such mechanism is the replay system that is disclosed in U.S. patent application Ser. No. 09/106,857, filed Jun. 30, 1998. The replay system must include a checking device to determine whether the instructions executed correctly or incorrectly.
Based on the foregoing, there is a need for a checking device for a replay system of a computer processor that speculatively schedules instructions.
SUMMARY OF THE INVENTION
One embodiment of the present invention is a computer processor that has a checker for receiving an instruction. The checker includes a scoreboard, an input for receiving an external replay signal, and decision logic coupled to the scoreboard and the input. The decision logic determines whether the instruction executed correctly based on both the scoreboard and the external replay signal.
REFERENCES:
patent: 5710902 (1998-01-01), Sheaffer et al.
patent: 5835745 (1998-11-01), Sager et al.
patent: 5966544 (1999-10-01), Sager
patent: 6065105 (2000-06-01), Zaidi et al.
patent: 0 612 012 (1994-08-01), None
patent: 2 317 724 (1998-04-01), None
patent: 99/31589 (1999-06-01), None
Merchant Amit A.
Sager David J.
Donaghue Larry D.
Intel Corporation
Kenyon & Kenyon
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