Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
1999-02-19
2001-01-23
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C327S359000
Reexamination Certificate
active
06177839
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a variable gain amplifier circuit. More to particularly, this invention relates to a variable gain amplifier circuit which is capable of implementing establishment of minimum gain without changing of DC voltage of output terminal at the time when the gain is to be variable.
DESCRIPTION OF THE PRIOR ART
In the variable gain amplifier circuit, when the amplifier circuit causes the gain to be changed from the minimum value to the maximum value, it is suitable that there is no change on the DC voltage of the output terminal. In the conventional variable gain amplifier circuit, there was the problem that when the amplifier circuit causes the gain to be changed in answer to the gain control signal, the DC voltage of the output terminal is changed in proportion to the gain. The Japanese Patent Application Laid-Open No. HEI 3-153133 discloses a variable gain amplifier circuit which copes with this problem.
FIG. 1
is a circuit view showing the variable gain amplifier circuit according to the conventional example disclosed in the Japanese Patent Application Laid-Open No. HEI 3-153113. The variable gain amplifier circuit shown in
FIG. 1
is provided with the input differential circuit, the gain control differential circuit, and the first and the second load resistors. The variable gain amplifier circuit is connected between the first power supply terminal
52
and the first and the second constant-current sources
37
,
38
, thus differential amplifying an input signal inputted to the first and the second input terminals
33
,
34
to be outputted in accordance with the gain control signal from the first and the second gain control terminals
31
,
32
.
The input differential circuit is provided with the first transistor
35
whose base is connected to the input terminal
33
, and the second transistor
36
whose base is connected to the input terminal
34
. Each emitter of the first transistor
35
and the second transistor
36
is connected to each other through the first emitter feedback resistor
41
, and is connected to the first and the second constant-current sources
37
,
38
. Numerals
39
,
40
denote earth terminals.
The gain control differential circuit is provided with the third, ninth, tenth, and fourth transistors
42
,
43
,
48
, and
49
whose respective bases are connected to the first gain control terminal
31
, and whose respective collectors are connected to the first and the second output terminals
53
and
54
and the fifth, sixth, seventh, and eighth transistors
44
,
45
,
46
, and
47
whose respective bases are connected to the second gain control terminal
32
. The respective emitters of the third, ninth, fifth, and sixth transistors
42
,
43
,
44
, and
45
are connected commonly to the collector of the first transistor
35
. The respective emitters of the seventh, eighth, tenth, and fourth transistors
46
,
47
,
48
, and
49
are connected commonly to the collector of the second transistor
36
. The respective collectors of the fifth and the seventh transistors
44
, and
46
are connected commonly to the first output terminal
53
. The respective collectors of the sixth and the eighth transistors
45
and
47
are connected commonly to the second output terminal
154
. The first load resistor
50
is connected between the respective collectors of the third, ninth, fifth, and seventh transistors
42
,
43
,
44
, and
46
and the first power supply terminal
52
. The second load resistor
51
is connected between respective collectors of the sixth, eighth, tenth, and fourth transistors
45
,
47
,
48
, and
49
and the first power supply terminal
52
.
Furthermore, there is equally established mutually the area of emitter region of the third, ninth, fifth, sixth, seventh, eighth, tenth, and fourth transistors
42
,
43
,
44
,
45
,
46
,
47
,
48
, and
49
.
The conventional variable gain amplifier circuit shown in
FIG. 1
operates as follows: Namely, signals inputted from the first and the second input terminal
33
,
34
are converted into current by the first and the second transistors
35
,
36
, thus being inputted commonly to the respective emitters of the third, ninth, fifth, and sixth transistors
42
,
43
,
44
, and
45
, and the seventh, eighth, tenth, and fourth transistors
46
,
47
,
48
, and
49
. The currents inputted to the respective emitters are shared among respective collectors of the third, ninth, fifth, and sixth transistors
42
,
43
,
44
, and
45
, and respective collectors of the seventh, eighth, tenth, and fourth transistors
46
,
47
,
48
, and
49
in accordance with the gain control voltage Vd from the gain control terminals
31
and
32
. The DC components of the collector current of the third, ninth, fifth, sixth, seventh, eighth, tenth, and fourth transistors
42
,
43
,
44
,
45
,
46
,
47
,
48
, and
49
are taken to be I
CQ3
, I
CQ9
, I
CQ5
,I
CQ6
, I
CQ7
, I
CQ8
, I
CQ10
, and I
CQ4
respectively, and the DC components of the collector current of the first and the second transistors
35
and
36
are taken to be Io. There is obtained following formulas:
I
CQ3
=
I
CQ9
=
I
CQ10
=
I
CQ4
=
Io
2
(
1
+
ⅇ
-
Vd
VT
)
I
CQ5
=
I
CQ6
=
I
CQ7
=
I
CQ8
=
Io
2
(
1
+
ⅇ
Vd
VT
)
Consequently, the DC current flowing through the first and the second load resistances
50
, and
51
becomes
I
CQ3
+I
CQ9
+I
CQ5
+I
CQ7
=I
CQ4
+I
CQ10
+I
CQ8
+I
CQ6
=Io
thus becoming constant, without depending on the gain control voltage Vd. Namely, when the gain to be variable, there is no change on the DC voltage of the output terminal.
Furthermore, the AC components of the collector current of the third, ninth, fifth, sixth, seventh, eighth, tenth, and fourth transistors
42
,
43
,
44
,
45
,
46
,
47
,
48
, and
49
are taken to be i
CQ3
, i
CQ9
, i
CQ5
, i
CQ6
, i
CQ7
, i
CQ8
, i
CQ10
, and i
CQ4
, and the AC component of the collector current of the first transistor
35
is taken to be io, there is obtained following formulas:
i
CQ3
=
i
CQ9
=
io
2
(
1
+
ⅇ
-
Vd
VT
)
=
-
i
CQ10
=
-
i
CQ4
i
CQ5
=
i
CQ6
=
io
2
(
1
+
ⅇ
Vd
VT
)
=
-
i
CQ7
=
-
i
CQ8
Consequently, the AC current flowing through the first and the second load resistors
50
and
51
becomes
i
CQ3
+
i
CQ9
+
i
CQ5
+
i
CQ7
=
io
1
+
ⅇ
-
Vd
VT
i
CQ4
+
i
CQ10
+
i
CQ8
+
i
CQ6
=
-
io
1
+
ⅇ
-
Vd
VT
Namely, the AC component of the collector current of the fifth and seventh transistors
44
and
46
, and the AC component of the collector current of the eighth and sixth transistors
47
and
45
are canceled completely with each other, thereby not contributing to the gain.
Next, there is taken with the load resistor as Rc, with the gain control voltage (gain control signal) as Vd, with the transfer conductance of the input differential circuit as Gm, with the thermal voltage as VT. At this time, the gain G of the variable gain amplifier circuit becomes
G
=
20
log
(
GmRc
)
-
20
log
(
1
+
ⅇ
-
Vd
VT
)
Here, when the gain control voltage increases in the negative direction, the minimum gain Gmin becomes
G
min=−∞
However, in the conventional variable gain amplifier circuit shown in
FIG. 1
, there is the problem that when the gain control voltage which is applied to the gain control terminal at the time when the gain is to be variable exceeds the regular range in the negative direction, thus the gain falls to the negative infinity.
The reason why there is obtained sum of the collector current of the fifth and the seventh transistors
44
and
46
or the collector current of the sixth and the eighth transistors
45
and
47
whose amplitude of AC component equals with each other, and whose phases are different mutually in the 180 degrees out of the fifth, sixth, seventh, and eighth transistors
44
,
45
,
46
, and
47
which operate at the time of minimum gain establishment with the same DC collector curren
Helfgott & Karas P.C.
NEC Corporation
Nguyen Khanh Van
Pascal Robert
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