Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-09-07
2001-05-08
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C257S529000
Reexamination Certificate
active
06228666
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices and a method of testing the same, and more specifically relates to a semiconductor integrated circuit device and a method of testing the same, wherein a test flow effecting decision as to whether a semiconductor integrated circuit device, such as an LSI chip conforms or is defective in a wafer test, and a defective article recognition circuit for realizing the test, flow are provided.
2. Description of the Prior Art
In recent years, in the field of multimedia equipments, for data processing of high degree attendant on processing of digital signals, devices of high performance have been required. On the other hand, in order to meet request of portability, specification which can not be easily attained by conventional semiconductor products is required in that semiconductor devices must be of small size and low consumption power. For such request, in order to intend low consumption power of a system and to reduce a board area, a hybrid IC such as a DRAM containing logic IC (hereinafter referred to as “eRAM (embedded RAM) logic IC”) in which DRAM and logic are formed in the form of one chip has been developed. The logic generally means a logic circuit where inputted data are subjected to logic operation and outputted, and in the logic of eRAM type, the operation result at the midway of the logic operation is once stored in the DRAM and the stored operation result is drawn afterward and subjected to the operation processing.
When such a hybrid IC is manufactured, a wafer test must be performed so as to effect decision that IC is conformed or defective before the shipment.
In general, a chip judged defective in the wafer test is marked with ink and then advanced to assembly in next process, and in the case of the hybrid IC, the DRAM unit and the logic unit must be tested in wafer test respectively. This is because a tester used in testing a general-purpose DRAM is different from that used in testing a logic IC, and in similar manner to this, in order to test the DRAM unit or the logic unit individually in the above-mentioned eRAM, the DRAM unit and the logic unit must be tested using individual testers.
When the DRAM unit and the logic unit are tested, if the ink marking to the defective chip is executed at finishing of test of either unit, a problem is produced that a wafer jig (probe card) may be flawed at testing of another unit. For example, consider that the test is performed in the order of the test of the DRAM unit and the test of the logic unit. Here the probe card is allowed to contact a needle being a part thereof with a pad within a chip and thereby performs test in giving an electric signal.
SUMMARY OF THE INVENTION
Since a semiconductor integrated circuit device and a method of testing the same in the prior art are constituted as above described, a chip judged defective in the test of the DRAM unit is once marked with ink by a tester for the DRAM unit. Then if the ink mark is shifted from the specified position and the ink flows to the upper side of the pad, there is a problem that the needle portion of the probe card may be broken when the tester is exchanged and the logic unit is tested.
Also a chip judged defective in the test on one hand (test of the DRAM unit or test of the logic unit) is only marked with ink and can appeal to the visual sensation. However, the tester at present can not recognize the ink mark and not effect decision that the chip is defective and need not be tested. Since the chip judged defective in the test on one hand may be tested again in the test on the other hand, there is a problem that the useless test time is required and the test time becomes long.
Since the logic IC or the general-purpose DRAM is originally judged conformed or defective using one tester, the above-mentioned problems can not be produced.
In order to solve the above-mentioned problems, an object of the present invention is to provide a semiconductor integrated circuit device and a method of testing the same, wherein a wafer test flow and a defective chip recognition unit to realize the test flow are provided.
In a semiconductor integrated circuit device according to the present invention, a DRAM unit and a logic unit are incorporated on the same semiconductor substrate and connected to each other, and a defective chip recognition circuit unit is provided so that at the time of testing the DRAM unit, if decision is effected that the DRAM unit can not be made conformed even by using a redundant circuit, the defective data is written in the defective chip recognition circuit. As a result, if the defective data are recognized at the previous stage of the test of the logic unit, since the chip judged defective in the test of the DRAM unit is not tested in the logic unit and the test can be finished, there is an effect that the unnecessary test time can be reduced.
Moreover, if a chip is defective in the test of the DRAM unit and judged conformed in the test of the logic unit, since the chip does not flow to assembly process being next process, there is an effect that the unnecessary cost can be reduced.
In a semiconductor integrated circuit device according to the present invention, the defective chip recognition circuit unit is formed on a surface of a semiconductor substrate, and has a defective chip recognition fuse and two pads connected externally on both ends of the defective chip recognition fuse respectively. As a result, since the defective chip recognition fuse can be deemed as a sort of resistance, a current flowing through the resistance between the two pads is measured and decision can be effected regarding whether the defective chip recognition fuse is blown out or not. Since the logic unit is not tested and the test can be finished, there is an effect that the above-mentioned unnecessary test time and the cost can be reduced.
In a semiconductor integrated circuit device according to the present invention, the defective chip recognition circuit unit is formed on a surface of a semiconductor substrate and has a defective chip recognition fuse and two pads connected externally on both ends of the defective chip recognition fuse respectively, and one of both ends is connected to the power source wiring within the chip and other end is connected to the pad. As a result, similar effect to the above-mentioned effect can be obtained and also there is an effect that the number of pad can be reduced.
In a semiconductor integrated circuit device according to the present invention, the defective chip recognition circuit unit is formed on a surface of a semiconductor substrate, and has a defective chip recognition fuse and two pads connected externally on both ends of the defective chip recognition fuse respectively, and one of both ends is connected to the GND wiring within the chip and other end is connected to the pad. As a result, similar effect to the above-mentioned effect can be obtained and also there is an effect that the pad number can be reduced.
In a semiconductor integrated circuit device according to the present invention, a redundancy fuse is included in a DRAM unit, and the redundancy fuse and a defective chip recognition fuse are made of the same material. As a result, since both fuses can be blown out in the same process, there is an effect that it can contribute to the process saving.
In a semiconductor integrated circuit device according to the present invention, a redundancy fuse and a defective chip recognition fuse are made of the same material formed in the same process. As a result, there is an effect that it can contribute to the saving of the number of process.
A method of testing a semiconductor integrated circuit device according to the present invention comprises a first step of effecting decision whether a DRAM unit is perfectly conformed or not, and effecting decision whether the DRAM unit judged imperfectly conformed can be made conformed or not using a redundancy circuit; a second step of effecting decision that t
Lee Calvin
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
Smith Matthew
LandOfFree
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