Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-06-03
2001-09-04
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090, C324S755090
Reexamination Certificate
active
06285204
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and more particularly to an improved method for testing semiconductor packages using oxide penetrating test contacts.
BACKGROUND OF THE INVENTION
Packaged semiconductor dice are tested several times during the manufacturing process. A probe test is conducted at the wafer level to test the gross functionality of the dice. Following singulation of the wafer and packaging of the individual dice, full functionality and burn-in tests are performed on the packaged dice. These tests are typically performed using testing apparatus that provide an electrical interface between the terminal leads on the package and external test circuitry.
For example, burn-in boards are adapted to hold a large number of packaged dice in a chamber with temperature cycling capability. The burn-in board includes electrical contacts that mate with the leads on the semiconductor packages to establish an electrical interconnection between the semiconductor dice and test circuitry. During the burn-in test the integrated circuits on the packaged dice are electrically tested at different temperatures.
One common semiconductor package for a single die is known as a small outline j-lead package (SOJ). A burn-in board for SOJ packages includes electrical test contacts that mate with the j-leads for the packages. Other standardized package lead configurations include gull wing, butt joint, integral standoff, pin grid array, ball grid array and land grid array. Standardized burn-in boards include test contacts for each of these types of package lead configurations.
One problem in making a temporary electrical connection to the leads on the semiconductor packages is caused by an oxide layer that forms on the surface of the package leads. The package leads are typically formed of a metal such as a nickel-iron alloy, a copper alloy or a copper clad stainless steel. Depending on the material, a metal oxide layer up to several hundred angstroms thick can form on the package leads. This oxide layer can result from environmental factors such as air and moisture.
In order to make a low resistance electrical connection with the package leads, the mating electrical contacts on the test apparatus can be constructed to scrub through the oxide layer and contact the underlying metal. This requires that the electrical contacts be configured for a lateral motion. This requirement can complicate the test apparatus and introduce additional process variables. In addition, the package leads can be damaged by the scrubbing motion.
Additionally, in order to make a low resistance electrical connection, the package leads are sometimes pressed against the electrical contacts on the test apparatus with a large contact force. In this case the package leads, or package, can be damaged by the force required to make the electrical connection. It would be advantageous to construct test contacts for semiconductor packages that do not require a large contact force or a scrubbing motion to make a low resistance electrical connection.
In view of the foregoing, it is an object of the present invention to provide an improved method for testing semiconductor packages using test contacts adapted to penetrate the oxide layer on the package leads with a minimal contact force. It is yet another object of the present invention to provide an improved test contact having an oxide penetrating conductive layer formed thereon. It is a still further object of the present invention to provide an improved method for forming a test contact with an oxide penetrating conductive layer. Other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for testing semiconductor packages using oxide penetrating test contacts is provided. The oxide penetrating test contacts are formed in a compliant shape and include a base layer and an external conductive layer having an abrasive grain material embedded therein. Suitable abrasive grain materials for the test contacts include diamond, synthetic diamond, diamond like carbon (DLC) and cubic boron nitride. The abrasive grain material and conductive layer can be formed on the test contacts using an electro-plating, chemical plating, powder metallurgy or vacuum deposition process.
The test contacts can be formed on a test apparatus such as a burn-in board for packaged semiconductor dice. The test contacts can be formed integrally with the test apparatus using an injection molding process. In an illustrative embodiment, the test contacts are formed as compliant spring segments. In addition, the test contacts can be formed with a shape for contacting standard lead configurations for semiconductor packages including: j-bend, gull wing, integral standoff, ball, pin or land package leads. During a test procedure, the package and package leads are pressed against the test contacts. This causes the conductive layers of the test contacts to penetrate an oxide coating on the package leads to form a conductive path from the package leads to external test circuitry.
REFERENCES:
patent: 3377514 (1968-04-01), Ruehlemann et al.
patent: 3596228 (1971-07-01), Reed, Jr.
patent: 3818415 (1974-06-01), Evans et al.
patent: 4770907 (1988-09-01), Kimura
patent: 5083967 (1992-01-01), DiFrancesco
patent: 5142785 (1992-09-01), Grewall et al.
patent: 5143523 (1992-09-01), Matarrese
patent: 5196107 (1993-03-01), Nakaoka et al.
patent: 5209613 (1993-05-01), Nishio
patent: 5402077 (1995-03-01), Agahdel et al.
patent: 5430614 (1995-07-01), DiFrancesco
patent: 5456404 (1995-10-01), Robinette, Jr. et al.
patent: 5471151 (1995-11-01), DiFrancesco
patent: 5527591 (1996-06-01), Crotzer
patent: 5729147 (1998-03-01), Schaff
patent: 6072324 (2000-06-01), Farnworth
Gratton Stephen A.
Karlsen Ernest
Micro)n Technology, Inc.
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