Electrical computers and digital processing systems: processing – Processing architecture – Vector processor
Reexamination Certificate
1998-08-11
2001-09-25
Follansbee, John A. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Vector processor
Reexamination Certificate
active
06295597
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of vector processor computers, and more specifically to a method and apparatus of long/extended-length integer arithmetic using an improved vector processor.
BACKGROUND OF THE INVENTION
Extended-length (or “long”) integer arithmetic is arithmetic that provides a number of significant bits (precision) that significantly exceeds the native, built-in capabilities of the computer being used. For example, a sixteen-bit processor can be used to handle arithmetic for the much larger numbers needed for scientific or financial spreadsheets or other calculations. An addition, for example, typically involves loading the lowest 16 bits from each operand in memory into internal registers, adding them together, storing the result into a result field in memory, then loading the next-significant 16 bits from each operand in memory into internal registers, adding them together along with the propagated carry from the first operation, storing the second result into the next-significant 16 bits of the result field in memory, and so on until the desired number of bits has been added, while propagating the carry from each operation into the next operation.
When taken to great lengths, such extended-length arithmetic can be used to compute pi to a million digits (for example), or for other desired applications carried out to as many significant bits as the programmer desires (within limits imposed by the storage capabilities of the computer and the time needed for the operations).
Vector processors have been used to improve the performance of a number of very-high-end computing applications such as weather forecasting and finite-element analysis. Many such applications use floating-point numbers and operations since they require only a correct magnitude (called the exponent) and a certain number of significant bits (called the mantissa or fraction). Therefore, many vector processors have been optimized for floating-point registers and operations. While suitable for many applications, floating-point operations are not suitable for applications requiring exact precision to hundreds or thousands of bits.
What is needed is improvements to the architecture and methods for vector processors and vector processing to improve extended-length (or “long”) integer arithmetic.
SUMMARY OF THE INVENTION
An apparatus and a method for extended-precision vector arithmetic is described capable of extremely long precision (i.e., precision to as many bits as a user desires or is limited to due to memory, disk-storage, or other resource constraints). Vector carry-out bits can be used as vector carry-in bits for successive operations.
In performing add or subtract operations on integers that are longer than the word size of the computer, the operands are broken into word-sized parts which are used as operands. A vector of long-integer numbers is thus broken into a series of sub-vectors, each having word-sized elements. Vector add or subtract operations are performed successively on the sub-vectors, starting with the lowest-order sub-vectors. Carry-out (or borrow-out) bits from a first vector operation are used as carry-in (or borrow-in) bits for a successive vector operation. In one embodiment, instructions are added to the instruction set of a vector processor to assist in propagating carry (or borrow) bits between components of long operands, and to assist users in accessing and controlling the carry (or borrow) bits.
One embodiment provides vector computer that includes a memory and an input-output subsystem including magnetic disk drives. The computer also includes vector element registers. Each vector element register can be selectively loaded with data from the memory. Each vector element register includes N elements, and each element has a plurality of bits. The computer also includes a vector carry register that has N bits. The computer also includes a vector arithmetic or logical functional unit having an input coupled to receive data operands from the respective elements of two vector element registers and the vector carry register, and operable to produce a result, wherein the result has successive elements and carry-out bits, and wherein each element of the result is based on an element from the first vector element register, a corresponding element from the second vector element register, and a corresponding bit from the vector carry register. A controller associated with the vector registers is responsive to program instructions to successively transmit one or more corresponding elements from each of the two vector element registers and one or more corresponding bits from the vector carry register to the functional unit as inputs, and to successively store results from the functional unit as elements into a vector element register.
In one such embodiment, the controller is adapted to transmit successive elements from any selected pair of the vector element registers and successive corresponding bits from the vector carry register as operands to the functional unit and to transmit results from the functional unit to successive elements of any selected one of the vector element registers and to successive corresponding bits of the vector carry register.
In another such embodiment, the functional unit is adapted to successively add pairs of elements of the vector element registers along with a corresponding carry-in bit from the vector carry register as operands to the functional unit and to successively output sum and carry-out results from the functional unit.
In yet another such embodiment, the functional unit is adapted to successively subtract an element of one vector element register and a corresponding borrow-in bit from the vector carry register from an element of another vector element register as operands to the functional unit and to successively output difference and borrow-out results from the functional unit.
In some embodiments, the controller is adapted to transmit two or more successive elements from each one of any selected pair of the vector element registers and two or more successive corresponding bits from the vector carry register as operands to the functional unit and to transmit two or more results from the functional unit to successive elements of any selected one of the vector element registers and to successive corresponding bits of the vector carry register.
In other embodiments, the controller is adapted to transmit four or more successive elements from each one of any selected pair of the vector element registers and four or more successive corresponding bits from the vector carry register as operands to the functional unit and to transmit four or more results from the functional unit to successive elements of any selected one of the vector element registers and to successive corresponding bits of the vector carry register.
Other aspects of the present invention provide a method for performing the above-described extended-precision arithmetic.
Yet other aspects of the present invention provide a vector processor for performing the above-described extended-precision arithmetic.
REFERENCES:
patent: 5396641 (1995-03-01), Iobst et al.
patent: 5652910 (1997-07-01), Boutaud et al.
patent: 5864703 (1999-06-01), Van Hook et al.
patent: 5966528 (1999-10-01), Wilkenson et al.
patent: 5991531 (1999-11-01), Song et al.
Moore William T.
Resnick David
Cray Inc.
Follansbee John A.
Schwegman Lundberg Woessner & Kluth P.A.
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