Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-02-03
2001-07-03
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000
Reexamination Certificate
active
06256005
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving voltage supply circuit and in particular, to an improved driving voltage supply circuit for a Liquid Crystal Display (LCD).
2. Background of the Related Art
FIG. 1
is a circuit diagram illustrating a related driving voltage supply circuit for an LCD panel. As shown therein, the related driving voltage supply circuit for an LCD panel includes an LCD controller
10
, and an input unit
11
that processes 6-bit color signals R, G, and B from the LCD controller
10
in each cycle of the clock signal CLK. The input unit
11
outputs color signal data R[
5
:
0
], G[
5
:
0
], and B[
5
:
0
] to a latch
13
. A shift register
12
comprises a plurality of shift registers connected in series, and shifts a shift register start pulse signal SSP in accordance with the clock signal CLK when the shift register start pulse signal SSP is inputted.
A latch unit
13
outputs a signal in accordance with an output enable signal OE when data corresponding to one line is inputted thereto wherein the output data from the input unit
11
is controlled by the output signal from the shift register
12
. A digital/analog converter
14
converts the digital color signal data from the latch unit
13
into an analog color signal, and an output buffer
15
buffers the output signal from the digital/analog converter
14
to a predetermined level.
When the color signals R, G, and B and synchronous signals H-SYNC and V-SYNC are inputted, the LCD controller
10
transmits the color signals synchronized with respect to the horizontal synchronous signal H-SYNC and vertical synchronous signal V-SYNC to the input unit
11
. The input unit
11
processes the 6-bit color signals from the LCD controller
10
in each cycle of the clock signal CLK. Therefore, the input unit
11
outputs the color signal data R[
5
:
0
], G[
5
:
0
], and B[
5
:
0
] of 18 bits, which were processed in 6 bits with respect to each of the color signals R, G, and B, to the latch unit
13
.
In the shift register
12
, which includes a plurality of shift registers (not shown), the SSP signal is sequentially shifted in accordance with the clock signal CLK when the SSP signal is applied to a first shift register (not shown). Whenever the SSP signal is outputted through the last shift register (not shown), the color signal from the input unit
11
is inputted into the latch unit
13
.
The latch unit
13
holds the color signal from the data input unit
11
in accordance with the output signal from the shift register
12
until the next color signal data is inputted. When the output enable signal OE is inputted, the color signal data from the input unit
11
is transmitted to the digital/analog converter
14
. The digital/analog converter
14
converts the digital color signal data from the latch unit
13
into analog color signals, and then transmits the analog color signals to the output buffer
15
. The output buffer
15
buffers the analog color signals R, G, and B to a predetermined level. The output voltage from the output buffer
15
is supplied to each pixel of the LCD panel, so that the LCD panel is activated by the color signal voltage.
In the related art, since the operation frequency of the shift register and the input frequency of the clock signal CLK are identical, the power consumption is increased. Accordingly, the circuit may be easily influenced by noise, which causes electromagnetic interference.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a driving voltage supply circuit for an LCD panel which overcomes the aforementioned problems encountered in the related art.
It is another object of the present invention to reduce the power consumption of an LCD panel.
Another object is to reduce a noise effect to the circuit.
A further object is to reduce an operational frequency of the shift register to one-half of an input clock frequency and driving the driving voltage supply circuit by using the thusly one-half-reduced frequency.
To achieve the above objects, there is provided a driving voltage supply circuit for an LCD panel which includes first and second input unit for separating and processing a data into an (2n+1)th data and a (2n)th data and outputting the processed data in accordance with a second control signal, a divider for dividing the clocks from the first and second input unit into the n-number of clocks and reducing an operational frequency of a shift register, a shift register for transmitting color signal data from the first and second input unit to the next circuit when the n-number of shift registers is sequentially shifted in accordance with a shift register start pulse signal whenever a clock which was divided is inputted, a latch unit for holding the data from the first and second input units in accordance with a shift register start signal from the shift register until the next color signal data is inputted, a digital/analog converter for converting a digital color signal data from the latch unit into an analog signal, and an output buffer for buffering an output signal from the digital/analog converter to a predetermined level for being outputted to the LCD panel.
The present invention may be achieved in parts or in a whole by a driving circuit for a display device, comprising: a first input unit that receives a first group of display data; a second input unit that receives a second group of display data; a divider coupled to receive a first clock signal of a first frequency, the divider changing the first clock signal by a prescribed amount to output a second clock signal of a second frequency, where the first and second frequencies are not equal to one another; a shift register unit coupled to the divider, and responsive to the second clock signal to shift an input control signal and to output a plurality of output signals; and an output device coupled to the first and second input units and the shift register unit such that the output device outputs the first and second groups of display data to the display device.
The present invention may be achieved in parts or in a whole by a method of operating a driving circuit of a display device, the method comprising the steps of: separating a plurality of display data into odd and even display data; converting a first clock signal to a second clock signal, where the first and second clock signal have different frequencies; controlling a transmission of even and odd display data in response to the second clock signal and a first control signal; and outputting the even and odd display data in response to a second control data.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
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patent: 5266936 (1993-11-01), Saitoh
patent: 5365284 (1994-11-01), Matsumoto et al.
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patent: 5675353 (1997-10-01), Tanaka et al.
patent: 5712651 (1998-01-01), Tomiyasu
patent: 5841430 (1998-10-01), Kurikko
patent: 5856816 (1999-01-01), Youn
patent: 5856818 (1999-01-01), Oh et al.
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Mengistu Amare
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